From patchwork Tue Nov 1 14:16:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 13026961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 886A5C433FE for ; Tue, 1 Nov 2022 14:19:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Vfd6ZlPx0ASGBEdMIeTK3gqfzX2Vt4j7Fo36JlQc1Zo=; b=b6arPXKtLC1roR NiW88Wx54W/tdSFeNytc+6Z+PJ0i/b1fIZuTEZenUTqK+NGpdlzPwdLCiGm5EKyKmwkReqqf2Jio5 RAzT7oCI+kwZp2AWoSzbUFHZHdH4vL4lv3urD1S86jmdZU4af6Sr5Xf54j37/PP6sEOnZbAdgTySP DI0xBl8qGhBRtcP2+j3wmFMEN8tkMrwbKDK6RRYFXk4l0UgT3fTA4fgvRMoVyBJOOX1HEt5gUihnS qcrWnbyYDFeBPsQmc5ZRKvzqMocNHmP5ej/7Ooa8Q9dMiaAx8JRaHOHNOQ+loizYOuU+nl8CdvwVc sA7igUxNrU6eeziG5FIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ops5w-005QZe-HC; Tue, 01 Nov 2022 14:18:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ops4u-005Q4A-Lb for linux-arm-kernel@lists.infradead.org; Tue, 01 Nov 2022 14:17:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 588F711FB; Tue, 1 Nov 2022 07:17:25 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 81A193F703; Tue, 1 Nov 2022 07:17:17 -0700 (PDT) From: Andre Przywara To: Jernej Skrabec , Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng , Mauro Carvalho Chehab , linux-media@vger.kernel.org Subject: [PATCH 7/9] ARM: dts: suniv: f1c100s: add CIR DT node Date: Tue, 1 Nov 2022 14:16:56 +0000 Message-Id: <20221101141658.3631342-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221101141658.3631342-1-andre.przywara@arm.com> References: <20221101141658.3631342-1-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221101_071720_768024_DEFBF1AF X-CRM114-Status: GOOD ( 10.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CIR (infrared receiver) controller in the Allwinner F1C100s series of SoCs is compatible to the ones used in other Allwinner SoCs. Add the DT node describing the resources of the controller. There are multiple possible pinmuxes, but none as them seem to be an obvious choice, so refrain from adding any pincontroller subnodes for now. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 2901c586971b4..d29b48f23b89a 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -251,6 +251,17 @@ pwm: pwm@1c21000 { status = "disabled"; }; + ir: ir@1c22c00 { + compatible = "allwinner,suniv-f1c100s-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c22c00 0x400>; + clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR>; + interrupts = <6>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>;