diff mbox series

[3/3] arm64: dts: imx8mq: Deduplicate PCIe clock-names property

Message ID 20221102212248.138284-3-marex@denx.de (mailing list archive)
State New, archived
Headers show
Series [1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property | expand

Commit Message

Marek Vasut Nov. 2, 2022, 9:22 p.m. UTC 
Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts           | 10 ++++------
 .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts   | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts   |  5 ++---
 .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq.dtsi              |  1 +
 5 files changed, 15 insertions(+), 21 deletions(-)

Comments

Alexander Stein Nov. 3, 2022, 7:56 a.m. UTC | #1 
Hi Marek,

Am Mittwoch, 2. November 2022, 22:22:48 CET schrieb Marek Vasut:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts           | 10 ++++------
>  .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts   | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts   |  5 ++---
>  .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi              |  1 +
>  5 files changed, 15 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index
> 2102e9b57697c..0e095bb176c5f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -355,10 +355,9 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
>  };
> @@ -368,10 +367,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	vpcie-supply = <&reg_pcie1>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index
> a91c136797f60..6376417e918c2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> @@ -245,20 +245,18 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	status = "okay";
>  };
> 
>  /* Intel Ethernet Controller I210/I211 */
>  &pcie1 {
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	fsl,max-link-speed = <1>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index
> 055031bba8c4b..200268660518d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> @@ -197,10 +197,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	status = "okay";
>  };
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index
> d7660eab68b94..344cfdaeb1d59 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> @@ -105,10 +105,9 @@ &led2 {
>  &pcie0 {
>  	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	epdev_on-supply = <&reg_vcc_3v3>;
>  	hard-wired = <1>;
>  	status = "okay";
> @@ -120,10 +119,9 @@ &pcie0 {
>   */
>  &pcie1 {
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	epdev_on-supply = <&reg_vcc_3v3>;
>  	hard-wired = <1>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index
> c6530e5c7fef5..c47e2d7235d3e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1529,6 +1529,7 @@ pcie0: pcie@33800000 {
>  			                <0 0 0 4 &gic GIC_SPI 122 
IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <0>;
> +			clock-names = "pcie", "pcie_bus", "pcie_phy", 
"pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIEPHY>,
>  			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,

For imx8mq.dtsi and imx8mq-tqma8mq-mba8mx.dts:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Thanks
Alexander
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 2102e9b57697c..0e095bb176c5f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -355,10 +355,9 @@  &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };
@@ -368,10 +367,9 @@  &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	vpcie-supply = <&reg_pcie1>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
index a91c136797f60..6376417e918c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -245,20 +245,18 @@  &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	status = "okay";
 };
 
 /* Intel Ethernet Controller I210/I211 */
 &pcie1 {
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	fsl,max-link-speed = <1>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
index 055031bba8c4b..200268660518d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
@@ -197,10 +197,9 @@  &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
index d7660eab68b94..344cfdaeb1d59 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
@@ -105,10 +105,9 @@  &led2 {
 &pcie0 {
 	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	epdev_on-supply = <&reg_vcc_3v3>;
 	hard-wired = <1>;
 	status = "okay";
@@ -120,10 +119,9 @@  &pcie0 {
  */
 &pcie1 {
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	epdev_on-supply = <&reg_vcc_3v3>;
 	hard-wired = <1>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index c6530e5c7fef5..c47e2d7235d3e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1529,6 +1529,7 @@  pcie0: pcie@33800000 {
 			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <0>;
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
 			power-domains = <&pgc_pcie>;
 			resets = <&src IMX8MQ_RESET_PCIEPHY>,
 			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,