| Message ID | 20221102215729.147335-2-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] dt-bindings: imx6q-pcie: Handle various clock configurations | expand |
On Wed, 02 Nov 2022 22:57:28 +0100, Marek Vasut wrote: > The i.MX SoCs have various power domain configurations routed into > the PCIe IP. MX6SX is the only one which contains 2 domains and also > uses power-domain-names. MX6QDL do not use any domains. All the rest > uses one domain and does not use power-domain-names anymore. > > Document all those configurations in the DT binding document. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: NXP Linux Team <linux-imx@nxp.com> > To: devicetree@vger.kernel.org > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- > 1 file changed, 34 insertions(+), 13 deletions(-) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ pcie@1ffc000: Unevaluated properties are not allowed ('disable-gpio' was unexpected) arch/arm/boot/dts/imx6dl-emcon-avari.dtb arch/arm/boot/dts/imx6q-emcon-avari.dtb pcie@33800000: clock-names:1: 'pcie_bus' was expected arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33800000: clock-names:2: 'pcie_aux' was expected arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb pcie@33800000: clock-names:2: 'pcie_bus' is not one of ['pcie_phy', 'pcie_aux'] arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb pcie@33800000: clock-names:3: 'pcie_aux' was expected arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33800000: clock-names:3: 'pcie_bus' is not one of ['pcie_inbound_axi', 'pcie_aux'] arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33800000: reset-names:0: 'pciephy' was expected arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dtb arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dtb pcie@33800000: reset-names:1: 'apps' was expected arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dtb arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dtb pcie@33800000: reset-names: ['apps', 'turnoff'] is too short arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dtb arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dtb pcie@33800000: resets: [[101, 26], [101, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dtb pcie@33800000: resets: [[25, 28], [25, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb pcie@33800000: resets: [[26, 28], [26, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb pcie@33800000: resets: [[27, 28], [27, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb pcie@33800000: resets: [[28, 28], [28, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb pcie@33800000: resets: [[29, 28], [29, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dtb pcie@33800000: resets: [[31, 28], [31, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb pcie@33800000: resets: [[34, 28], [34, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb pcie@33800000: resets: [[40, 28], [40, 29]] is too short arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb pcie@33800000: resets: [[48, 26], [48, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dtb pcie@33800000: resets: [[59, 26], [59, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb pcie@33800000: resets: [[63, 26], [63, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-evk.dtb pcie@33800000: resets: [[69, 26], [69, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb pcie@33800000: resets: [[75, 26], [75, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dtb pcie@33800000: resets: [[82, 26], [82, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dtb pcie@33800000: resets: [[85, 26], [85, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb pcie@33800000: resets: [[96, 26], [96, 27]] is too short arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dtb pcie@33800000: Unevaluated properties are not allowed ('clock-names', 'reset-names', 'resets' were unexpected) arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dtb arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dtb arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-evk.dtb arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dtb arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dtb arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dtb arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-evk.dtb arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dtb pcie@33800000: Unevaluated properties are not allowed ('epdev_on-supply', 'hard-wired' were unexpected) arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb pcie@33800000: Unevaluated properties are not allowed ('reset-names', 'resets' were unexpected) arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-ctouch2.dtb arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dtb arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dtb arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dtb arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dtb arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dtb arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dtb arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dtb arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dtb pcie@33c00000: 'bus-range' is a required property arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33c00000: clock-names:1: 'pcie_bus' was expected arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33c00000: clock-names:3: 'pcie_aux' was expected arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33c00000: clock-names:3: 'pcie_bus' is not one of ['pcie_inbound_axi', 'pcie_aux'] arch/arm64/boot/dts/freescale/imx8mq-evk.dtb arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dtb arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dtb arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dtb pcie@33c00000: Unevaluated properties are not allowed ('epdev_on-supply', 'hard-wired' were unexpected) arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dtb
Hi Marek, Am Mittwoch, 2. November 2022, 22:57:28 CET schrieb Marek Vasut: > The i.MX SoCs have various power domain configurations routed into > the PCIe IP. MX6SX is the only one which contains 2 domains and also > uses power-domain-names. MX6QDL do not use any domains. All the rest > uses one domain and does not use power-domain-names anymore. > > Document all those configurations in the DT binding document. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: NXP Linux Team <linux-imx@nxp.com> > To: devicetree@vger.kernel.org > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- > 1 file changed, 34 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index > 1cfea8ca72576..fc8d4d7b80b38 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -68,19 +68,6 @@ properties: > description: A phandle to an fsl,imx7d-pcie-phy node. Additional > required properties for imx7d-pcie and imx8mq-pcie. > > - power-domains: > - items: > - - description: The phandle pointing to the DISPLAY domain for > - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > - imx8mq-pcie. > - - description: The phandle pointing to the PCIE_PHY power domains > - for imx6sx-pcie. > - > - power-domain-names: > - items: > - - const: pcie > - - const: pcie_phy > - > resets: > maxItems: 3 > description: Phandles to PCIe-related reset lines exposed by SRC > @@ -241,6 +228,40 @@ allOf: > - const: pcie_bus > - const: pcie_phy > > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx6sx-pcie > + then: > + properties: > + power-domains: > + items: > + - description: The phandle pointing to the DISPLAY domain for > + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > + imx8mq-pcie. > + - description: The phandle pointing to the PCIE_PHY power > domains + for imx6sx-pcie. > + power-domain-names: > + items: > + - const: pcie > + - const: pcie_phy > + else: > + if: > + not: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx6q-pcie > + - fsl,imx6qp-pcie > + then: > + properties: > + power-domains: > + description: | > + The phandle pointing to the DISPLAY domain for imx6sx-pcie, > to + PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. + Doesn't it makes more sense to keep the power-domains descriptions in the common part on top, as before, but adjust minItems/maxItems for each compatible? Regards, Alexander > examples: > - | > #include <dt-bindings/clock/imx6qdl-clock.h>
On Thu, Nov 3, 2022 at 3:29 AM Alexander Stein <alexander.stein@ew.tq-group.com> wrote: > > Hi Marek, > > Am Mittwoch, 2. November 2022, 22:57:28 CET schrieb Marek Vasut: > > The i.MX SoCs have various power domain configurations routed into > > the PCIe IP. MX6SX is the only one which contains 2 domains and also > > uses power-domain-names. MX6QDL do not use any domains. All the rest > > uses one domain and does not use power-domain-names anymore. > > > > Document all those configurations in the DT binding document. > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > --- > > Cc: Fabio Estevam <festevam@gmail.com> > > Cc: Lucas Stach <l.stach@pengutronix.de> > > Cc: Richard Zhu <hongxing.zhu@nxp.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Shawn Guo <shawnguo@kernel.org> > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: NXP Linux Team <linux-imx@nxp.com> > > To: devicetree@vger.kernel.org > > --- > > .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- > > 1 file changed, 34 insertions(+), 13 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index > > 1cfea8ca72576..fc8d4d7b80b38 100644 > > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > > @@ -68,19 +68,6 @@ properties: > > description: A phandle to an fsl,imx7d-pcie-phy node. Additional > > required properties for imx7d-pcie and imx8mq-pcie. > > > > - power-domains: > > - items: > > - - description: The phandle pointing to the DISPLAY domain for > > - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > > - imx8mq-pcie. > > - - description: The phandle pointing to the PCIE_PHY power domains > > - for imx6sx-pcie. > > - > > - power-domain-names: > > - items: > > - - const: pcie > > - - const: pcie_phy > > - > > resets: > > maxItems: 3 > > description: Phandles to PCIe-related reset lines exposed by SRC > > @@ -241,6 +228,40 @@ allOf: > > - const: pcie_bus > > - const: pcie_phy > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: fsl,imx6sx-pcie > > + then: > > + properties: > > + power-domains: > > + items: > > + - description: The phandle pointing to the DISPLAY domain for > > + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > > + imx8mq-pcie. > > + - description: The phandle pointing to the PCIE_PHY power > > domains + for imx6sx-pcie. > > + power-domain-names: > > + items: > > + - const: pcie > > + - const: pcie_phy > > + else: > > + if: > > + not: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - fsl,imx6q-pcie > > + - fsl,imx6qp-pcie > > + then: > > + properties: > > + power-domains: > > + description: | > > + The phandle pointing to the DISPLAY domain for imx6sx-pcie, > > to + PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. + > > Doesn't it makes more sense to keep the power-domains descriptions in the > common part on top, as before, but adjust minItems/maxItems for each > compatible? Yes. Keep properties defined at the top level. Rob
On 11/3/22 13:32, Rob Herring wrote: > On Thu, Nov 3, 2022 at 3:29 AM Alexander Stein > <alexander.stein@ew.tq-group.com> wrote: >> >> Hi Marek, >> >> Am Mittwoch, 2. November 2022, 22:57:28 CET schrieb Marek Vasut: >>> The i.MX SoCs have various power domain configurations routed into >>> the PCIe IP. MX6SX is the only one which contains 2 domains and also >>> uses power-domain-names. MX6QDL do not use any domains. All the rest >>> uses one domain and does not use power-domain-names anymore. >>> >>> Document all those configurations in the DT binding document. >>> >>> Signed-off-by: Marek Vasut <marex@denx.de> >>> --- >>> Cc: Fabio Estevam <festevam@gmail.com> >>> Cc: Lucas Stach <l.stach@pengutronix.de> >>> Cc: Richard Zhu <hongxing.zhu@nxp.com> >>> Cc: Rob Herring <robh+dt@kernel.org> >>> Cc: Shawn Guo <shawnguo@kernel.org> >>> Cc: linux-arm-kernel@lists.infradead.org >>> Cc: NXP Linux Team <linux-imx@nxp.com> >>> To: devicetree@vger.kernel.org >>> --- >>> .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- >>> 1 file changed, 34 insertions(+), 13 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index >>> 1cfea8ca72576..fc8d4d7b80b38 100644 >>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >>> @@ -68,19 +68,6 @@ properties: >>> description: A phandle to an fsl,imx7d-pcie-phy node. Additional >>> required properties for imx7d-pcie and imx8mq-pcie. >>> >>> - power-domains: >>> - items: >>> - - description: The phandle pointing to the DISPLAY domain for >>> - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and >>> - imx8mq-pcie. >>> - - description: The phandle pointing to the PCIE_PHY power domains >>> - for imx6sx-pcie. >>> - >>> - power-domain-names: >>> - items: >>> - - const: pcie >>> - - const: pcie_phy >>> - >>> resets: >>> maxItems: 3 >>> description: Phandles to PCIe-related reset lines exposed by SRC >>> @@ -241,6 +228,40 @@ allOf: >>> - const: pcie_bus >>> - const: pcie_phy >>> >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: fsl,imx6sx-pcie >>> + then: >>> + properties: >>> + power-domains: >>> + items: >>> + - description: The phandle pointing to the DISPLAY domain for >>> + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and >>> + imx8mq-pcie. >>> + - description: The phandle pointing to the PCIE_PHY power >>> domains + for imx6sx-pcie. >>> + power-domain-names: >>> + items: >>> + - const: pcie >>> + - const: pcie_phy >>> + else: >>> + if: >>> + not: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - fsl,imx6q-pcie >>> + - fsl,imx6qp-pcie >>> + then: >>> + properties: >>> + power-domains: >>> + description: | >>> + The phandle pointing to the DISPLAY domain for imx6sx-pcie, >>> to + PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. + >> >> Doesn't it makes more sense to keep the power-domains descriptions in the >> common part on top, as before, but adjust minItems/maxItems for each >> compatible? > > Yes. Keep properties defined at the top level. The problem I keep running into here is that if I apply patch like below (basically what you and Alex are suggesting), I get this warning: arch/arm64/boot/dts/freescale/imx8mm-board.dtb: pcie@33800000: power-domains: [[86]] is too short I think that's because power-domains: contains items: and to validate that imx8mm.dtsi with pcie@33800000 { power-domains = <&pgc_pcie>; };, I would need to get rid of those items: ? Which is what I did in the aforementioned patch for imx8m, that's why I removed it from the common part. diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 12c7baba489aa..ec5e8dfe541ea 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -68,6 +68,18 @@ properties: description: A phandle to an fsl,imx7d-pcie-phy node. Additional required properties for imx7d-pcie and imx8mq-pcie. + power-domains: + items: + - description: The phandle pointing to the DISPLAY domain for + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and + imx8mq-pcie. + - description: The phandle pointing to the PCIE_PHY power domains + for imx6sx-pcie. + power-domain-names: + items: + - const: pcie + - const: pcie_phy + resets: maxItems: 2 description: Phandles to PCIe-related reset lines exposed by SRC @@ -235,16 +247,11 @@ allOf: then: properties: power-domains: - items: - - description: The phandle pointing to the DISPLAY domain for - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and - imx8mq-pcie. - - description: The phandle pointing to the PCIE_PHY power domains - for imx6sx-pcie. + minItems: 2 + maxItems: 2 power-domain-names: - items: - - const: pcie - - const: pcie_phy + minItems: 2 + maxItems: 2 else: if: not: @@ -257,9 +264,8 @@ allOf: then: properties: power-domains: - description: | - The phandle pointing to the DISPLAY domain for imx6sx-pcie, to - PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. + minItems: 1 + maxItems: 1 - if: properties:
Hi Marek, Am Donnerstag, 3. November 2022, 17:25:46 CET schrieb Marek Vasut: > On 11/3/22 13:32, Rob Herring wrote: > > On Thu, Nov 3, 2022 at 3:29 AM Alexander Stein > > > > <alexander.stein@ew.tq-group.com> wrote: > >> Hi Marek, > >> > >> Am Mittwoch, 2. November 2022, 22:57:28 CET schrieb Marek Vasut: > >>> The i.MX SoCs have various power domain configurations routed into > >>> the PCIe IP. MX6SX is the only one which contains 2 domains and also > >>> uses power-domain-names. MX6QDL do not use any domains. All the rest > >>> uses one domain and does not use power-domain-names anymore. > >>> > >>> Document all those configurations in the DT binding document. > >>> > >>> Signed-off-by: Marek Vasut <marex@denx.de> > >>> --- > >>> Cc: Fabio Estevam <festevam@gmail.com> > >>> Cc: Lucas Stach <l.stach@pengutronix.de> > >>> Cc: Richard Zhu <hongxing.zhu@nxp.com> > >>> Cc: Rob Herring <robh+dt@kernel.org> > >>> Cc: Shawn Guo <shawnguo@kernel.org> > >>> Cc: linux-arm-kernel@lists.infradead.org > >>> Cc: NXP Linux Team <linux-imx@nxp.com> > >>> To: devicetree@vger.kernel.org > >>> --- > >>> > >>> .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- > >>> 1 file changed, 34 insertions(+), 13 deletions(-) > >>> > >>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > >>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index > >>> 1cfea8ca72576..fc8d4d7b80b38 100644 > >>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > >>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > >>> > >>> @@ -68,19 +68,6 @@ properties: > >>> description: A phandle to an fsl,imx7d-pcie-phy node. Additional > >>> > >>> required properties for imx7d-pcie and imx8mq-pcie. > >>> > >>> - power-domains: > >>> - items: > >>> - - description: The phandle pointing to the DISPLAY domain for > >>> - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > >>> - imx8mq-pcie. > >>> - - description: The phandle pointing to the PCIE_PHY power domains > >>> - for imx6sx-pcie. > >>> - > >>> - power-domain-names: > >>> - items: > >>> - - const: pcie > >>> - - const: pcie_phy > >>> - > >>> > >>> resets: > >>> maxItems: 3 > >>> description: Phandles to PCIe-related reset lines exposed by SRC > >>> > >>> @@ -241,6 +228,40 @@ allOf: > >>> - const: pcie_bus > >>> - const: pcie_phy > >>> > >>> + - if: > >>> + properties: > >>> + compatible: > >>> + contains: > >>> + const: fsl,imx6sx-pcie > >>> + then: > >>> + properties: > >>> + power-domains: > >>> + items: > >>> + - description: The phandle pointing to the DISPLAY domain > >>> for > >>> + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie > >>> and > >>> + imx8mq-pcie. > >>> + - description: The phandle pointing to the PCIE_PHY power > >>> domains + for imx6sx-pcie. > >>> + power-domain-names: > >>> + items: > >>> + - const: pcie > >>> + - const: pcie_phy > >>> + else: > >>> + if: > >>> + not: > >>> + properties: > >>> + compatible: > >>> + contains: > >>> + enum: > >>> + - fsl,imx6q-pcie > >>> + - fsl,imx6qp-pcie > >>> + then: > >>> + properties: > >>> + power-domains: > >>> + description: | > >>> + The phandle pointing to the DISPLAY domain for > >>> imx6sx-pcie, > >>> to + PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. > >>> + > >> > >> Doesn't it makes more sense to keep the power-domains descriptions in the > >> common part on top, as before, but adjust minItems/maxItems for each > >> compatible? > > > > Yes. Keep properties defined at the top level. > > The problem I keep running into here is that if I apply patch like below > (basically what you and Alex are suggesting), I get this warning: > > arch/arm64/boot/dts/freescale/imx8mm-board.dtb: pcie@33800000: > power-domains: [[86]] is too short I guess you need this: > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -65,6 +65,7 @@ properties: required properties for imx7d-pcie and imx8mq-pcie. power-domains: + minItems: 1 items: - description: The phandle pointing to the DISPLAY domain for imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and I have a similar WIP change on my tree which add 'minItems: 1' to power- domains and also sets 'maxItems: 1' to power-domains for everything being not fsl,imx6sx-pcie. Best regards, Alexander > I think that's because power-domains: contains items: and to validate > that imx8mm.dtsi with pcie@33800000 { power-domains = <&pgc_pcie>; };, I > would need to get rid of those items: ? Which is what I did in the > aforementioned patch for imx8m, that's why I removed it from the common > part. > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index 12c7baba489aa..ec5e8dfe541ea 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -68,6 +68,18 @@ properties: > description: A phandle to an fsl,imx7d-pcie-phy node. Additional > required properties for imx7d-pcie and imx8mq-pcie. > > + power-domains: > + items: > + - description: The phandle pointing to the DISPLAY domain for > + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > + imx8mq-pcie. > + - description: The phandle pointing to the PCIE_PHY power domains > + for imx6sx-pcie. > + power-domain-names: > + items: > + - const: pcie > + - const: pcie_phy > + > resets: > maxItems: 2 > description: Phandles to PCIe-related reset lines exposed by SRC > @@ -235,16 +247,11 @@ allOf: > then: > properties: > power-domains: > - items: > - - description: The phandle pointing to the DISPLAY domain for > - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > - imx8mq-pcie. > - - description: The phandle pointing to the PCIE_PHY power > domains > - for imx6sx-pcie. > + minItems: 2 > + maxItems: 2 > power-domain-names: > - items: > - - const: pcie > - - const: pcie_phy > + minItems: 2 > + maxItems: 2 > else: > if: > not: > @@ -257,9 +264,8 @@ allOf: > then: > properties: > power-domains: > - description: | > - The phandle pointing to the DISPLAY domain for > imx6sx-pcie, to > - PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. > + minItems: 1 > + maxItems: 1 > > - if: > properties:
On 11/4/22 08:19, Alexander Stein wrote: > Hi Marek, > > Am Donnerstag, 3. November 2022, 17:25:46 CET schrieb Marek Vasut: >> On 11/3/22 13:32, Rob Herring wrote: >>> On Thu, Nov 3, 2022 at 3:29 AM Alexander Stein >>> >>> <alexander.stein@ew.tq-group.com> wrote: >>>> Hi Marek, >>>> >>>> Am Mittwoch, 2. November 2022, 22:57:28 CET schrieb Marek Vasut: >>>>> The i.MX SoCs have various power domain configurations routed into >>>>> the PCIe IP. MX6SX is the only one which contains 2 domains and also >>>>> uses power-domain-names. MX6QDL do not use any domains. All the rest >>>>> uses one domain and does not use power-domain-names anymore. >>>>> >>>>> Document all those configurations in the DT binding document. >>>>> >>>>> Signed-off-by: Marek Vasut <marex@denx.de> >>>>> --- >>>>> Cc: Fabio Estevam <festevam@gmail.com> >>>>> Cc: Lucas Stach <l.stach@pengutronix.de> >>>>> Cc: Richard Zhu <hongxing.zhu@nxp.com> >>>>> Cc: Rob Herring <robh+dt@kernel.org> >>>>> Cc: Shawn Guo <shawnguo@kernel.org> >>>>> Cc: linux-arm-kernel@lists.infradead.org >>>>> Cc: NXP Linux Team <linux-imx@nxp.com> >>>>> To: devicetree@vger.kernel.org >>>>> --- >>>>> >>>>> .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- >>>>> 1 file changed, 34 insertions(+), 13 deletions(-) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >>>>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index >>>>> 1cfea8ca72576..fc8d4d7b80b38 100644 >>>>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >>>>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >>>>> >>>>> @@ -68,19 +68,6 @@ properties: >>>>> description: A phandle to an fsl,imx7d-pcie-phy node. Additional >>>>> >>>>> required properties for imx7d-pcie and imx8mq-pcie. >>>>> >>>>> - power-domains: >>>>> - items: >>>>> - - description: The phandle pointing to the DISPLAY domain for >>>>> - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and >>>>> - imx8mq-pcie. >>>>> - - description: The phandle pointing to the PCIE_PHY power domains >>>>> - for imx6sx-pcie. >>>>> - >>>>> - power-domain-names: >>>>> - items: >>>>> - - const: pcie >>>>> - - const: pcie_phy >>>>> - >>>>> >>>>> resets: >>>>> maxItems: 3 >>>>> description: Phandles to PCIe-related reset lines exposed by SRC >>>>> >>>>> @@ -241,6 +228,40 @@ allOf: >>>>> - const: pcie_bus >>>>> - const: pcie_phy >>>>> >>>>> + - if: >>>>> + properties: >>>>> + compatible: >>>>> + contains: >>>>> + const: fsl,imx6sx-pcie >>>>> + then: >>>>> + properties: >>>>> + power-domains: >>>>> + items: >>>>> + - description: The phandle pointing to the DISPLAY domain >>>>> for >>>>> + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie >>>>> and >>>>> + imx8mq-pcie. >>>>> + - description: The phandle pointing to the PCIE_PHY power >>>>> domains + for imx6sx-pcie. >>>>> + power-domain-names: >>>>> + items: >>>>> + - const: pcie >>>>> + - const: pcie_phy >>>>> + else: >>>>> + if: >>>>> + not: >>>>> + properties: >>>>> + compatible: >>>>> + contains: >>>>> + enum: >>>>> + - fsl,imx6q-pcie >>>>> + - fsl,imx6qp-pcie >>>>> + then: >>>>> + properties: >>>>> + power-domains: >>>>> + description: | >>>>> + The phandle pointing to the DISPLAY domain for >>>>> imx6sx-pcie, >>>>> to + PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. >>>>> + >>>> >>>> Doesn't it makes more sense to keep the power-domains descriptions in the >>>> common part on top, as before, but adjust minItems/maxItems for each >>>> compatible? >>> >>> Yes. Keep properties defined at the top level. >> >> The problem I keep running into here is that if I apply patch like below >> (basically what you and Alex are suggesting), I get this warning: >> >> arch/arm64/boot/dts/freescale/imx8mm-board.dtb: pcie@33800000: >> power-domains: [[86]] is too short > > I guess you need this: >> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -65,6 +65,7 @@ properties: > required properties for imx7d-pcie and imx8mq-pcie. > > power-domains: > + minItems: 1 > items: > - description: The phandle pointing to the DISPLAY domain for > imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > > I have a similar WIP change on my tree which add 'minItems: 1' to power- > domains and also sets 'maxItems: 1' to power-domains for everything being not > fsl,imx6sx-pcie. This is what I was missing, thanks.
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 1cfea8ca72576..fc8d4d7b80b38 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -68,19 +68,6 @@ properties: description: A phandle to an fsl,imx7d-pcie-phy node. Additional required properties for imx7d-pcie and imx8mq-pcie. - power-domains: - items: - - description: The phandle pointing to the DISPLAY domain for - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and - imx8mq-pcie. - - description: The phandle pointing to the PCIE_PHY power domains - for imx6sx-pcie. - - power-domain-names: - items: - - const: pcie - - const: pcie_phy - resets: maxItems: 3 description: Phandles to PCIe-related reset lines exposed by SRC @@ -241,6 +228,40 @@ allOf: - const: pcie_bus - const: pcie_phy + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-pcie + then: + properties: + power-domains: + items: + - description: The phandle pointing to the DISPLAY domain for + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and + imx8mq-pcie. + - description: The phandle pointing to the PCIE_PHY power domains + for imx6sx-pcie. + power-domain-names: + items: + - const: pcie + - const: pcie_phy + else: + if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + then: + properties: + power-domains: + description: | + The phandle pointing to the DISPLAY domain for imx6sx-pcie, to + PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. + examples: - | #include <dt-bindings/clock/imx6qdl-clock.h>
The i.MX SoCs have various power domain configurations routed into the PCIe IP. MX6SX is the only one which contains 2 domains and also uses power-domain-names. MX6QDL do not use any domains. All the rest uses one domain and does not use power-domain-names anymore. Document all those configurations in the DT binding document. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Fabio Estevam <festevam@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> To: devicetree@vger.kernel.org --- .../bindings/pci/fsl,imx6q-pcie.yaml | 47 ++++++++++++++----- 1 file changed, 34 insertions(+), 13 deletions(-)