From patchwork Fri Nov 4 13:09:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13031737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68184C43219 for ; Fri, 4 Nov 2022 13:11:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=k9HZrWjeb2bCqzYNEXCPLTTnAhJYrmyIIjWVHYvQNA8=; b=X6qU1myom1kHCZ l3fcTHOUKzPgtjfIMB8PVTI598qdItusrjRQ3N1nMK+Xmkuy3z1z3SMXA1PZgGJO9XSgiMrbQrXFG Vspq51EaEZmYoWLvMdcJJvROnQFnmCSOkJOHu4C8qFIv+EOFyvIUoDMuLG8qcFpGR+gAIZcQ2Giog 4J5dUFoHuxR5Heg4wgwXMFL09pgTSuQqDoaO8xq7n5v8VY2c7IeAFo0Ad9G7u38bkAgiFb5Lr4eWx 83KlOctB0wAGc+Njh81RrccrppeSAcAXbAedvwFzDrV4GvuRsgeeUwYFWUqT6PyHhLCAJVtHqtW8s 5xKnwMkbAa4P3hLkKgFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqwSe-003ZuK-Ja; Fri, 04 Nov 2022 13:10:16 +0000 Received: from phobos.denx.de ([2a01:238:438b:c500:173d:9f52:ddab:ee01]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqwSL-003ZrV-Hl for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 13:09:59 +0000 Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 3E08E8523F; Fri, 4 Nov 2022 14:09:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1667567395; bh=gh11G3AaEBtlTEMnz3njAdootS4aFQyGxnfH+IR/9eM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bKHbigH2dwST5stI8Lj/xtkxvACBE3+uiPbM6iKU+TbmqgLgccKRDIIXn1ejgCuFt 1oR/Z4TarJcmpwd4pirLwLvNoFfOkmgFWNMSJoJS+Dvr46b3lT4ORnunbDDQ6/39yZ UpJRXMOfpjfxrXdadAkz4z85Jo2vRyprnG96/AMA/UMcc34Sk6/POxLgCgSYN85U0c 9uOT2VYBBiB6XHqvFuCjwVkDcGp7kx3/dLJ9gNR4AXs7s+P8OALT1dGejbiBa0s7t6 HTXTPLkBSu89AXFFbmR7UPPfJMm3XvjG5hNNjZARK0zAElhbuk/FBxn+siYt1jh3vB Nk9BsERXPI4/Q== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexander Stein , Fabio Estevam , Peng Fan , Richard Zhu , Shawn Guo , NXP Linux Team Subject: [PATCH v2 3/3] arm64: dts: imx8mq: Deduplicate PCIe clock-names property Date: Fri, 4 Nov 2022 14:09:42 +0100 Message-Id: <20221104130942.103190-3-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104130942.103190-1-marex@denx.de> References: <20221104130942.103190-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_060957_910313_6A0E9077 X-CRM114-Status: GOOD ( 12.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Move the PCIe clock-names property from various DTs into SoC dtsi to reduce duplication. In case of a couple of boards, reorder the clock so they match the order in yaml DT bindings. Reviewed-by: Alexander Stein # imx8mq.dtsi, imx8mq-tqma8mq-mba8mx.dts Signed-off-by: Marek Vasut --- Cc: Fabio Estevam Cc: Peng Fan Cc: Richard Zhu Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Alex - Add default pcie clock entry into dtsi - Fix the Ultra board --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 ++++------ .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 5 ++--- .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++++++++ 6 files changed, 28 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 82387b9cb8000..3fb3f8d6b9478 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -355,10 +355,9 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; vph-supply = <&vgen5_reg>; status = "okay"; }; @@ -368,10 +367,9 @@ &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; vpcie-supply = <®_pcie1>; vph-supply = <&vgen5_reg>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index a91c136797f60..6376417e918c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -245,20 +245,18 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; status = "okay"; }; /* Intel Ethernet Controller I210/I211 */ &pcie1 { clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; fsl,max-link-speed = <1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 055031bba8c4b..200268660518d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -197,10 +197,9 @@ &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index d7660eab68b94..344cfdaeb1d59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -105,10 +105,9 @@ &led2 { &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; epdev_on-supply = <®_vcc_3v3>; hard-wired = <1>; status = "okay"; @@ -120,10 +119,9 @@ &pcie0 { */ &pcie1 { clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; epdev_on-supply = <®_vcc_3v3>; hard-wired = <1>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 4e05120c62d41..74a7a589a3296 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -551,10 +551,9 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE1_AUX>; vph-supply = <&vgen5_reg>; status = "okay"; }; @@ -564,10 +563,9 @@ &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&clk IMX8MQ_CLK_PCIE2_AUX>; vph-supply = <&vgen5_reg>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index b14dbf2ffb9a7..fbcfa0c9468fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1529,6 +1529,11 @@ pcie0: pcie@33800000 { <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, @@ -1566,6 +1571,11 @@ pcie1: pcie@33c00000 { <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <1>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,