| Message ID | 20221104170417.232132-2-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC,v3,1/3] dt-bindings: imx6q-pcie: Handle various clock configurations | expand |
On 04/11/2022 18:04, Marek Vasut wrote: > The i.MX SoCs have various power domain configurations routed into > the PCIe IP. MX6SX is the only one which contains 2 domains and also > uses power-domain-names. MX6QDL do not use any domains. All the rest > uses one domain and does not use power-domain-names anymore. > > Document all those configurations in the DT binding document. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: NXP Linux Team <linux-imx@nxp.com> > To: devicetree@vger.kernel.org > --- > V2: - Keep the power-domains description in the main section > V3: - Move power-domains back where they were originally (fixes V2) > - Do not use else: in allOf section > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 31 ++++++++++++++++++- > 1 file changed, 30 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index 44c65d3ec07b9..5d731aca34b4d 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -67,13 +67,13 @@ properties: > required properties for imx7d-pcie and imx8mq-pcie. > > power-domains: > + minItems: 1 > items: > - description: The phandle pointing to the DISPLAY domain for > imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and > imx8mq-pcie. > - description: The phandle pointing to the PCIE_PHY power domains > for imx6sx-pcie. > - > power-domain-names: > items: > - const: pcie > @@ -222,6 +222,35 @@ allOf: > - const: pcie_bus > - const: pcie_aux > > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx6sx-pcie > + then: > + properties: > + power-domains: > + minItems: 2 > + maxItems: 2 > + power-domain-names: > + minItems: 2 > + maxItems: 2 > + > + - if: > + not: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx6q-pcie > + - fsl,imx6qp-pcie This is confusing... your previous entry fsl,imx6sx-pcie falls into this one, because it is a if-not-then. This also does not really match your commit msg. > + then: > + properties: > + power-domains: > + minItems: 1 Drop minItems, it cannot be less than 1. > + maxItems: 1 > + power-domain-names: false > + > examples: > - | > #include <dt-bindings/clock/imx6qdl-clock.h> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 44c65d3ec07b9..5d731aca34b4d 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -67,13 +67,13 @@ properties: required properties for imx7d-pcie and imx8mq-pcie. power-domains: + minItems: 1 items: - description: The phandle pointing to the DISPLAY domain for imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and imx8mq-pcie. - description: The phandle pointing to the PCIE_PHY power domains for imx6sx-pcie. - power-domain-names: items: - const: pcie @@ -222,6 +222,35 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-pcie + then: + properties: + power-domains: + minItems: 2 + maxItems: 2 + power-domain-names: + minItems: 2 + maxItems: 2 + + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + then: + properties: + power-domains: + minItems: 1 + maxItems: 1 + power-domain-names: false + examples: - | #include <dt-bindings/clock/imx6qdl-clock.h>
The i.MX SoCs have various power domain configurations routed into the PCIe IP. MX6SX is the only one which contains 2 domains and also uses power-domain-names. MX6QDL do not use any domains. All the rest uses one domain and does not use power-domain-names anymore. Document all those configurations in the DT binding document. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> To: devicetree@vger.kernel.org --- V2: - Keep the power-domains description in the main section V3: - Move power-domains back where they were originally (fixes V2) - Do not use else: in allOf section --- .../bindings/pci/fsl,imx6q-pcie.yaml | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-)