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[108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:21 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 7/7] ARM: dts: imx: Update i.MXRT1050.dtsi compatibles Date: Mon, 7 Nov 2022 02:15:11 -0500 Message-Id: <20221107071511.2764628-8-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231522_798689_F818DADE X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remove unused compatibles from i.MXRT1050.dtsi. Change GPT clock-names to match documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- arch/arm/boot/dts/imxrt1050.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi index 03e6a858a7be..8d79de239046 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -29,7 +29,7 @@ osc3M: osc3M { soc { lpuart1: serial@40184000 { - compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imxrt1050-lpuart"; reg = <0x40184000 0x4000>; interrupts = <20>; clocks = <&clks IMXRT1050_CLK_LPUART1>; @@ -40,7 +40,6 @@ lpuart1: serial@40184000 { iomuxc: pinctrl@401f8000 { compatible = "fsl,imxrt1050-iomuxc"; reg = <0x401f8000 0x4000>; - fsl,mux_mask = <0x7>; }; anatop: anatop@400d8000 { @@ -83,7 +82,7 @@ edma1: dma-controller@400e8000 { }; usdhc1: mmc@402c0000 { - compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + compatible = "fsl,imxrt1050-usdhc"; reg = <0x402c0000 0x4000>; interrupts = <110>; clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, @@ -150,11 +149,11 @@ gpio5: gpio@400c0000 { }; gpt: timer@401ec000 { - compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt"; reg = <0x401ec000 0x4000>; interrupts = <100>; - clocks = <&osc3M>; - clock-names = "per"; + clocks = <&osc3M>, <&osc3M>; + clock-names = "ipg", "per"; }; }; };