From patchwork Mon Nov 7 17:24:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13034915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 745A2C433FE for ; Mon, 7 Nov 2022 17:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=llS/gWTU5+FCRG3kMt4CB/qi6Z+83c156n1oDRzxK/w=; b=ksQLp/lWj0XhOh vSTtDZfng5LO1EgK6DtLaBZe9rO+GD8arNP8ZxiqVXamLVbTgsn5SL/JWX4OXRwaxnghnbjBDg7Dg fv8+xfwL7pB14mFkfnobHOuCBMfBA6AwtxbSnLC6MEkim5Astx9VvMVbVoy8/quvjoqazhRq28v1r xAEy9Sl3fwjuLQ0A3obG4nLZMZs1gN1tVK2fBrvZifG2TPHV+ToiVE+HSb6fr6Uj3WryyeWJyct6k 5bOzkmUFX1uouvtPjVNua+224HL+ZeqYmLY8W7hZaVFKbst/Z2coBE69Hsd+QJlAB7yEFUMMSb3zb jKSovSVozuNTcCgn6lsw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1os5r5-00Gea3-MQ; Mon, 07 Nov 2022 17:24:15 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1os5r1-00GeYR-Ki for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2022 17:24:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DD058611E1; Mon, 7 Nov 2022 17:24:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D41B5C433D6; Mon, 7 Nov 2022 17:24:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667841850; bh=JTqHVMAnLRDuS59/KQho5vfw/08ICMwl26xYT9jZGaw=; h=From:To:Cc:Subject:Date:From; b=ONmwvSgnof641xcPHZJQt7W0jk86EeE4MQOAclEKzHYLBnvJH5ELMrPOk8YVKE1yA aMH/sHT2BeR3VrBYqqXYXQ5pVrUrBlWnrrsD8UAS3MaSrLRsNB+tfxswOlXTNBMEZZ xgjOGE8WUFpYlEIjbtpxmXa8GYSFu2+uA4xwP1FpxCqbI9G6TySOQBWhVFEHi2ETKO f8/fB49Hr2YdWwTtDn7grF3dYW+LoMadhTUlDmtDsl1tllfUp4d4knsNS/EoXxuDTM MZHq6GsOHirb5guK2iVMvkpYdVYP0Jw2oZLT+eOCWtkyr6p5kX0lPeqYmAP7kFDdL0 UROcCJ4UCrCPw== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Ard Biesheuvel , Catalin Marinas , Will Deacon , Mark Rutland , Marc Zyngier , Eric Biggers , "Jason A . Donenfeld" , Kees Cook , Suzuki K Poulose , Adam Langley Subject: [PATCH v2] arm64: Enable data independent timing (DIT) in the kernel Date: Mon, 7 Nov 2022 18:24:00 +0100 Message-Id: <20221107172400.1851434-1-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6920; i=ardb@kernel.org; h=from:subject; bh=JTqHVMAnLRDuS59/KQho5vfw/08ICMwl26xYT9jZGaw=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBjaT8vsX5vWi+Uk2D/eR/+1Os7/WkNHOPumKXI3PHY X9ScIbaJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCY2k/LwAKCRDDTyI5ktmPJNmhC/ wLkHECASV8fUtHk33mgENb14RuvJjs0v3tmnS9WD7vusxr4LWq5mKVV4zbJhl4hXtOcGBhFVmWId6G GH+/tQvcCmopb4o/P5YKclovQctqZ5BvMqbmxFXhHbpXey3ILW8NiLpoi9td+KniW6OIkacl7nszT9 W0E+o3vfj9ebwbCIF74ctz4tDAIC2bj8hFBeevmBnKwkxs+4vLFWY/FjiSI0WdUf1ef94RYEBhoNI+ jpFS/sCKNBbs6XnW0GxHRfJqT89v5YDQnHZhhhZxdlSuh14xyUwOBEft+iQUkPdCfgmyE0AW3nxn+o oMe1g0czn6sO6xE4iL4Z16t0hOTSdMd+0kjfcZd8r2tHaycQ+3nh63hntLC5IUVqxGGtlI4mTm3nyd cusxrZLWWicfCbxuu0Mg3gnSQnmeGvM9nIs2hT9rIxXgO/7VgCVV1O03GbfUsVMVi9cOeEGCjUTvgk ApHSun+MFeyUm5aL8qS6LzoQCIW6bimD7s0Z141vS2sAY= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221107_092411_793863_FCA9AF51 X-CRM114-Status: GOOD ( 25.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ARM architecture revision v8.4 introduces a data independent timing control (DIT) which can be set at any exception level, and instructs the CPU to avoid optimizations that may result in a correlation between the execution time of certain instructions and the value of the data they operate on. The DIT bit is part of PSTATE, and is therefore context switched as usual, given that it becomes part of the saved program state (SPSR) when taking an exception. We have also defined a hwcap for DIT, and so user space can discover already whether or nor DIT is available. This means that, as far as user space is concerned, DIT is wired up and fully functional. In the kernel, however, we never bothered with DIT: we disable at it boot (i.e., INIT_PSTATE_EL1 has DIT cleared) and ignore the fact that we might run with DIT enabled if user space happened to set it. Currently, we have no idea whether or not running privileged code with DIT disabled on a CPU that implements support for it may result in a side channel that exposes privileged data to unprivileged user space processes, so let's be cautious and just enable DIT while running in the kernel if supported by all CPUs. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: Marc Zyngier Cc: Eric Biggers Cc: Jason A. Donenfeld Cc: Kees Cook Cc: Suzuki K Poulose Cc: Adam Langley Link: https://lore.kernel.org/all/YwgCrqutxmX0W72r@gmail.com/ Signed-off-by: Ard Biesheuvel --- v2: - enable DIT on resume-from-suspend path - tidy up some issues spotted by Eric - avoid some code duplication in SET_PSTATE_xxx macro definitions - tweak the commit log so that it doesn't read as if we are fixing an actual vulnerability arch/arm64/include/asm/cpufeature.h | 5 +++++ arch/arm64/include/asm/sysreg.h | 12 ++++++++---- arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++ arch/arm64/kernel/entry.S | 3 +++ arch/arm64/kernel/suspend.c | 2 ++ arch/arm64/tools/cpucaps | 1 + 6 files changed, 36 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f73f11b5504254be..f44579bca9f8107e 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -875,6 +875,11 @@ static inline bool cpu_has_pan(void) ID_AA64MMFR1_EL1_PAN_SHIFT); } +static inline bool cpu_has_dit(void) +{ + return cpus_have_const_cap(ARM64_HAS_DIT); +} + #ifdef CONFIG_ARM64_AMU_EXTN /* Check whether the cpu supports the Activity Monitors Unit (AMU) */ extern bool cpu_has_amu_feat(int cpu); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7d301700d1a93692..1f3f52ce407fe942 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -90,20 +90,24 @@ */ #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) #define PSTATE_Imm_shift CRm_shift +#define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) #define PSTATE_PAN pstate_field(0, 4) #define PSTATE_UAO pstate_field(0, 3) #define PSTATE_SSBS pstate_field(3, 1) +#define PSTATE_DIT pstate_field(3, 2) #define PSTATE_TCO pstate_field(3, 4) -#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) +#define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) +#define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) +#define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) +#define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) +#define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) +#define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6062454a90674317..74ceec411ea8b597 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2077,6 +2077,11 @@ static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); } +static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) +{ + set_pstate_dit(1); +} + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2640,6 +2645,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .cpu_enable = cpu_trap_el0_impdef, }, + { + .desc = "Data independent timing control (DIT)", + .capability = ARM64_HAS_DIT, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .sys_reg = SYS_ID_AA64PFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64PFR0_EL1_DIT_SHIFT, + .field_width = 4, + .min_field_value = ID_AA64PFR0_EL1_DIT_IMP, + .matches = has_cpuid_feature, + .cpu_enable = cpu_enable_dit, + }, {}, }; diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e28137d64b7688e2..11cb99c4d298784d 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -197,6 +197,9 @@ alternative_cb_end .endm .macro kernel_entry, el, regsize = 64 + .if \el == 0 + alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT + .endif .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 .endif diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c index 8b02d310838f9240..3032a82ea51a19f7 100644 --- a/arch/arm64/kernel/suspend.c +++ b/arch/arm64/kernel/suspend.c @@ -60,6 +60,8 @@ void notrace __cpu_suspend_exit(void) * PSTATE was not saved over suspend/resume, re-enable any detected * features that might not have been set correctly. */ + if (cpu_has_dit()) + set_pstate_dit(1); __uaccess_enable_hw_pan(); /* diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index f1c0347ec31a85c7..a86ee376920a08dd 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -20,6 +20,7 @@ HAS_CNP HAS_CRC32 HAS_DCPODP HAS_DCPOP +HAS_DIT HAS_E0PD HAS_ECV HAS_EPAN