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Mon, 14 Nov 2022 17:40:42 -0600 From: Tanmay Shah To: , , , , CC: , , , , , Tanmay Shah Subject: [PATCH v11 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Date: Mon, 14 Nov 2022 15:39:35 -0800 Message-ID: <20221114233940.2096237-2-tanmay.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114233940.2096237-1-tanmay.shah@amd.com> References: <20221114233940.2096237-1-tanmay.shah@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT097:EE_|SJ0PR12MB5408:EE_ X-MS-Office365-Filtering-Correlation-Id: 33fe2285-b0e7-4090-741d-08dac699a644 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UEM2syqeeM8YDzoZ4e+bZBiIYgmYc7I5cmsRV+zH6j8Z0yukKQsB4SSsWrEqetxIf2loVhC1XC5LdpuS38l8Cl2CsJSzM+quXlMQ+PUOQBRp+5DLZEqWyP3aISOHAHhBYcAhfpmrLtNVhE1896IA8CBB19c/TOHGhKPHlJXBiRoQOTIxwNdfAFz3wlgpDGalLTE/+Y6LqVQyT+d8pYXOOY2bJNIxDqXV19dN9oN1y6g+3xedDhJ/U3VPuhATDYny1GIwBUKImTccf4jCfLRuXdevQYJE8omNArt0HcRJFKCdCdv/QjshsLSaC0jIzWd5aqrJdA7OGSGwgvQVKxN79eowBDD4NbC8Zejz1sxjUgpidVTyyg2eXgxDgHT8d5t8NDnHUhkF1H5cghTGOxuEjKWaLwFHFOBj6T3ee1VquOOiYVx+J2GrC375hkV8BMMYDj9pi7e9kn/899xNNvgfTOGuMPXRe44xOT2t7N3Yp1EAeJH/47RshXM6H27o287Y2uu6i9UWkVl6HadXy7t0M8O61lCYEX0VFkovcn2nv/CMzBVWXPQlGR4duchV3RZTCkDNGivc44OysEAfHJjBOzgojdXQos+JgrsfRh1lYsY9UfxbOg5Q4FndzG0Moq4B5sFEl0tRMWu+pXgq8Zn40NodY20P8MmBDNzdwQ7HhkpjmK6t7yWO8jWBF/t/MoVOBkIs71FnJ5+hPxR/urVrejj7sjiZ83n2JPG0iGHgiYoir9bNCWUCU9tZ1MHh+FofgOVupvHbqrGlr4Ey3ZXJkFfcVtaAxt08ESaVVXDPxLL7TQkDeiZ0PjJ9WwxQVDrMKT2wsoGVBo6VcsWfxBan+Bffag0py9VEXuuFrh5AVGw20pIQ1qftQSGZ24mUtrAf X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(376002)(396003)(136003)(451199015)(46966006)(40470700004)(36840700001)(4326008)(336012)(70586007)(8676002)(8936002)(36756003)(70206006)(44832011)(26005)(186003)(5660300002)(1076003)(41300700001)(2616005)(316002)(82740400003)(86362001)(40480700001)(40460700003)(82310400005)(83380400001)(81166007)(426003)(47076005)(36860700001)(2906002)(356005)(6666004)(966005)(6636002)(478600001)(110136005)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2022 23:40:44.6427 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33fe2285-b0e7-4090-741d-08dac699a644 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5408 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221114_154052_755780_37E137C0 X-CRM114-Status: GOOD ( 21.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem (cluster). Signed-off-by: Tanmay Shah Reviewed-by: Rob Herring --- Changes in v11: - rename binding filename to match with compatible string - change $id: value accordingly as well Changes in v10: - rename example node to remoteproc Changes in v9: - remove power-domains property description - fix nitpicks in description of other properties Changes in v8: - Add 'items:' for sram property Changes in v7: - Add minItems in sram property Changes in v6: - Add maxItems to sram and memory-region property Changes in v5: - Add constraints of the possible values of xlnx,cluster-mode property - fix description of power-domains property for r5 core - Remove reg, address-cells and size-cells properties as it is not required - Fix description of mboxes property - Add description of each memory-region and remove old .txt binding link reference in the description Changes in v4: - Add memory-region, mboxes and mbox-names properties in example Changes in v3: - None .../remoteproc/xlnx,zynqmp-r5fss.yaml | 135 ++++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml new file mode 100644 index 000000000000..9f677367dd9f --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx R5F processor subsystem + +maintainers: + - Ben Levinsky + - Tanmay Shah + +description: | + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for + real-time processing based on the Cortex-R5F processor core from ARM. + The Cortex-R5F processor implements the Arm v7-R architecture and includes a + floating-point unit that implements the Arm VFPv3 instruction set. + +properties: + compatible: + const: xlnx,zynqmp-r5fss + + xlnx,cluster-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: | + The RPU MPCore can operate in split mode (Dual-processor performance), Safety + lock-step mode(Both RPU cores execute the same code in lock-step, + clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while + core 1 runs normally). The processor does not support dynamic configuration. + Switching between modes is only permitted immediately after a processor reset. + If set to 1 then lockstep mode and if 0 then split mode. + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. + In summary, + 0: split mode + 1: lockstep mode (default) + 2: single cpu mode + +patternProperties: + "^r5f-[a-f0-9]+$": + type: object + description: | + The RPU is located in the Low Power Domain of the Processor Subsystem. + Each processor includes separate L1 instruction and data caches and + tightly coupled memories (TCM). System memory is cacheable, but the TCM + memory space is non-cacheable. + + Each RPU contains one 64KB memory and two 32KB memories that + are accessed via the TCM A and B port interfaces, for a total of 128KB + per processor. In lock-step mode, the processor has access to 256KB of + TCM memory. + + properties: + compatible: + const: xlnx,zynqmp-r5f + + power-domains: + maxItems: 1 + + mboxes: + minItems: 1 + items: + - description: mailbox channel to send data to RPU + - description: mailbox channel to receive data from RPU + + mbox-names: + minItems: 1 + items: + - const: tx + - const: rx + + sram: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 + items: + maxItems: 1 + description: | + phandles to one or more reserved on-chip SRAM regions. Other than TCM, + the RPU can execute instructions and access data from the OCM memory, + the main DDR memory, and other system memories. + + The regions should be defined as child nodes of the respective SRAM + node, and should be defined as per the generic bindings in + Documentation/devicetree/bindings/sram/sram.yaml + + memory-region: + description: | + List of phandles to the reserved memory regions associated with the + remoteproc device. This is variable and describes the memories shared with + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg + vrings, ...). This reserved memory region will be allocated in DDR memory. + minItems: 1 + maxItems: 8 + items: + - description: region used for RPU firmware image section + - description: vdev buffer + - description: vring0 + - description: vring1 + additionalItems: true + + required: + - compatible + - power-domains + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + remoteproc { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware 0x7>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + + r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware 0x8>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; + }; +... diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..618024cbb20d 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -6,6 +6,12 @@ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H +#define PD_RPU_0 7 +#define PD_RPU_1 8 +#define PD_R5_0_ATCM 15 +#define PD_R5_0_BTCM 16 +#define PD_R5_1_ATCM 17 +#define PD_R5_1_BTCM 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24