From patchwork Tue Nov 15 14:38:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13043776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C649BC43219 for ; Tue, 15 Nov 2022 14:40:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yiA9ko08hqjtV3BiNX7paR/UF4uS8vLxGfitDFgPM5g=; b=UeFzJ/mqgYcgY1 55X0aiz4nRV605WWtOty05kkVpFWZtjMca4Orz5W7bN38GSBaX4dplsRK56vHFxbnxtCRJy2HVDj2 F8EFHXDeL/EEF8fVzFTv5vDAqeAPtjsoXPVUPhZjMw+Pgja7ZnjSGHzwhQd1dJOAaMiWt2kcO4YqN GTz+f6wXwec+7X3hsc9hBr6FjbduZSbw60UM7FQlG95x6SD8bdSDmuTvhun7GT/Fy0Vgwd2CP2Q1I QsDa1riVDcDc9CaPaRfYo6RT6mDuzs1FkSD1V9sXKHo+xnWQghHlMYhyQhSPp16Uy0hw1cJ06L0Pj hR/FkZw3AloK2j6nfRow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oux5a-00BwzU-8I; Tue, 15 Nov 2022 14:39:02 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oux5D-00BwjS-Ip for linux-arm-kernel@lists.infradead.org; Tue, 15 Nov 2022 14:38:41 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 499BFB818DF; Tue, 15 Nov 2022 14:38:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64239C433D6; Tue, 15 Nov 2022 14:38:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668523116; bh=HNbJ+tDk02pmuGw+eDNQkmefUnrBu7GqX1KBub1xE/w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JkGtlUF0QQn/3KH18MVnn9U328B5SweZmtj5K6GGDiaYkvrRp1Y2hiDtoXM4J55cn SHflMwzOkN8mszfqQgK/MZYRtrksmto964BGqoaPkHXIuOdluIF66VbTd4yTzpSbSk etWHD0fv489zDhIehQmok6YQ1yi7alH0NcSK5T9o+0ygi4cstmGdBSGWyu9d2Wt9H8 nBh0+bd1UM3UwWn+9WywKUIy/qdi9c39OlNc5vf6QjDtaohpbGpO7dfOJNbHo76JRm MOi+4d90BNPA8aH0Uprj8EgtOoEmo6WF88CLfWCp957KIuZY/F7d9RkCoPQ63Ps4TA HtcRFnX6MLjdA== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Catalin Marinas , Will Deacon , Mark Rutland , Anshuman Khandual , Joey Gouly Subject: [PATCH 2/3] arm64: mm: Handle LVA support as a CPU feature Date: Tue, 15 Nov 2022 15:38:23 +0100 Message-Id: <20221115143824.2798908-3-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221115143824.2798908-1-ardb@kernel.org> References: <20221115143824.2798908-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9081; i=ardb@kernel.org; h=from:subject; bh=HNbJ+tDk02pmuGw+eDNQkmefUnrBu7GqX1KBub1xE/w=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBjc6RdQoOeyvN2FaQDjdNMyixpNXflWQqj57RRbLqG pBSUxQyJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCY3OkXQAKCRDDTyI5ktmPJEq3C/ 4tTrTX0WhWfPsokgOtRRT1XGSh49V5qDD1Xfo93pZlIZyO1D64lqRc+SRQN1xuifMKE0A5LoAoeiSU 3sFrFLh1cZdRRMIys9ZhJPavspLnk5plDArUwgWsEC++stFZWMuup9FTGXcAdMGXjH531ReQneo5P0 oiTwCrmkdASL9CCPq8fZ3o31SyPRfBpHBFhr1Von63ZAsc2gmVmmhPAdmWVg1hqf/zcn/9z80PSmPz Q5lqjvANTxQOAT2xmV6cl4kc8zb4l9XP3oaOdZIuM2jiPjiJksjz3z5Gf+8II8RPRoPHb5fDyNqbE9 BCBFNRwqv/4Xe0+Iv/enW3bquCcubk/RBUyCi8li8fr8KVufBcFjsTBDQ3Hm9Xsni6QJwUiZYmftdp S0fF8fwHWpSHuj1oVElM5x3bvQyXKTscgCX8MaGDJ/Pgw8/u4zDGm1pS11RlG3SfEjPhTq5l0fxEkU wZMy/A9qP56TaHN5rIk+GOorzlVgFCjQm0h5nl/kX0Xcs= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221115_063839_932646_86EEEDB7 X-CRM114-Status: GOOD ( 25.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, we detect CPU support for 52-bit virtual addressing (LVA) extremely early, before creating the kernel page tables or enabling the MMU. We cannot override the feature this early, and so large virtual addressing is always enabled on CPUs that implement support for it if the software support for it was enabled at build time. It also means we rely on non-trivial code in asm to deal with this feature. Given that both the ID map and the TTBR1 mapping of the kernel image are guaranteed to be 48-bit addressable, it is not actually necessary to enable support this early, and instead, we can model it as a CPU feature. That way, we can rely on code patching to get the correct TCR.T1SZ values programmed on secondary boot and suspend from resume. On the primary boot path, we simply enable the MMU with 48-bit virtual addressing initially, and update TCR.T1SZ from C code if LVA is supported, right before creating the kernel mapping. Given that TTBR1 still points to reserved_pg_dir at this point, updating TCR.T1SZ should be safe without the need for explicit TLB maintenance. Since this gets rid of all accesses to the vabits_actual variable from asm code that occurred before TCR.T1SZ had been programmed, we no longer have a need for this variable, and we can replace it with a C expression that produces the correct value directly, based on the value of TCR.T1SZ. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/memory.h | 4 +++- arch/arm64/kernel/cpufeature.c | 13 +++++++++++ arch/arm64/kernel/head.S | 24 +++----------------- arch/arm64/kernel/pi/map_kernel.c | 12 ++++++++++ arch/arm64/kernel/sleep.S | 3 --- arch/arm64/mm/mmu.c | 5 ---- arch/arm64/mm/proc.S | 16 ++++++------- arch/arm64/tools/cpucaps | 1 + 8 files changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index a4e1d832a15a2d7a..20e15c3f4589bd38 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -183,9 +183,11 @@ #include #include #include +#include #if VA_BITS > 48 -extern u64 vabits_actual; +// For reasons of #include hell, we can't use TCR_T1SZ_OFFSET/TCR_T1SZ_MASK here +#define vabits_actual (64 - ((read_sysreg(tcr_el1) >> 16) & 63)) #else #define vabits_actual ((u64)VA_BITS) #endif diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index eca9df123a8b354b..b44aece5024c3e2d 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2654,6 +2654,19 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .cpu_enable = cpu_trap_el0_impdef, }, +#ifdef CONFIG_ARM64_VA_BITS_52 + { + .desc = "52-bit Virtual Addressing (LVA)", + .capability = ARM64_HAS_LVA, + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, + .sys_reg = SYS_ID_AA64MMFR2_EL1, + .sign = FTR_UNSIGNED, + .field_width = 4, + .field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT, + .matches = has_cpuid_feature, + .min_field_value = ID_AA64MMFR2_EL1_VARange_52, + }, +#endif {}, }; diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 3b3c5e8e84af890e..6abf513189c7ebc9 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -80,7 +80,6 @@ * x20 primary_entry() .. __primary_switch() CPU boot mode * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 * x22 create_idmap() .. start_kernel() ID map VA of the DT blob - * x25 primary_entry() .. start_kernel() supported VA size * x28 create_idmap() callee preserved temp register */ SYM_CODE_START(primary_entry) @@ -95,14 +94,6 @@ SYM_CODE_START(primary_entry) * On return, the CPU will be ready for the MMU to be turned on and * the TCR will have been set. */ -#if VA_BITS > 48 - mrs_s x0, SYS_ID_AA64MMFR2_EL1 - tst x0, #0xf << ID_AA64MMFR2_EL1_VARange_SHIFT - mov x0, #VA_BITS - mov x25, #VA_BITS_MIN - csel x25, x25, x0, eq - mov x0, x25 -#endif bl __cpu_setup // initialise processor b __primary_switch SYM_CODE_END(primary_entry) @@ -406,11 +397,6 @@ SYM_FUNC_START_LOCAL(__primary_switched) mov x0, x20 bl set_cpu_boot_mode_flag -#if VA_BITS > 48 - adr_l x8, vabits_actual // Set this early so KASAN early init - str x25, [x8] // ... observes the correct value - dc civac, x8 // Make visible to booting secondaries -#endif #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) bl kasan_early_init #endif @@ -525,9 +511,6 @@ SYM_FUNC_START_LOCAL(secondary_startup) mov x20, x0 // preserve boot mode bl finalise_el2 bl __cpu_secondary_check52bitva -#if VA_BITS > 48 - ldr_l x0, vabits_actual -#endif bl __cpu_setup // initialise processor adrp x1, swapper_pg_dir adrp x2, idmap_pg_dir @@ -628,10 +611,9 @@ SYM_FUNC_END(__enable_mmu) SYM_FUNC_START(__cpu_secondary_check52bitva) #if VA_BITS > 48 - ldr_l x0, vabits_actual - cmp x0, #52 - b.ne 2f - +alternative_if_not ARM64_HAS_LVA + ret +alternative_else_nop_endif mrs_s x0, SYS_ID_AA64MMFR2_EL1 and x0, x0, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT) cbnz x0, 2f diff --git a/arch/arm64/kernel/pi/map_kernel.c b/arch/arm64/kernel/pi/map_kernel.c index 2bbf017147830bbe..3504e3266b02f636 100644 --- a/arch/arm64/kernel/pi/map_kernel.c +++ b/arch/arm64/kernel/pi/map_kernel.c @@ -122,6 +122,15 @@ static bool __init arm64_early_this_cpu_has_e0pd(void) ID_AA64MMFR2_EL1_E0PD_SHIFT); } +static bool __init arm64_early_this_cpu_has_lva(void) +{ + u64 mmfr2; + + mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); + return cpuid_feature_extract_unsigned_field(mmfr2, + ID_AA64MMFR2_EL1_VARange_SHIFT); +} + static bool __init arm64_early_this_cpu_has_pac(void) { u64 isar1, isar2; @@ -274,6 +283,9 @@ asmlinkage void __init early_map_kernel(u64 boot_status, void *fdt) /* Parse the command line for CPU feature overrides */ init_feature_override(boot_status, fdt, chosen); + if (VA_BITS > VA_BITS_MIN && arm64_early_this_cpu_has_lva()) + sysreg_clear_set(tcr_el1, TCR_T1SZ_MASK, TCR_T1SZ(VA_BITS)); + if (IS_ENABLED(CONFIG_ARM64_WXN) && cpuid_feature_extract_unsigned_field(arm64_sw_feature_override.val, ARM64_SW_FEATURE_OVERRIDE_NOWXN)) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index 97c9de57725dfddb..617f78ad43a185c2 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -101,9 +101,6 @@ SYM_FUNC_END(__cpu_suspend_enter) SYM_CODE_START(cpu_resume) bl init_kernel_el bl finalise_el2 -#if VA_BITS > 48 - ldr_l x0, vabits_actual -#endif bl __cpu_setup /* enable the MMU early - so we can access sleep_save_stash by va */ adrp x1, swapper_pg_dir diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index a9714b00f5410d7d..63fb62e16a1f8873 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -45,11 +45,6 @@ int idmap_t0sz __ro_after_init; -#if VA_BITS > 48 -u64 vabits_actual __ro_after_init = VA_BITS_MIN; -EXPORT_SYMBOL(vabits_actual); -#endif - u64 kimage_voffset __ro_after_init; EXPORT_SYMBOL(kimage_voffset); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 98531775ff529dc8..02818fa6aded3218 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -400,8 +400,6 @@ SYM_FUNC_END(idmap_kpti_install_ng_mappings) * * Initialise the processor for turning the MMU on. * - * Input: - * x0 - actual number of VA bits (ignored unless VA_BITS > 48) * Output: * Return in x0 the value of the SCTLR_EL1 register. */ @@ -426,20 +424,20 @@ SYM_FUNC_START(__cpu_setup) mair .req x17 tcr .req x16 mov_q mair, MAIR_EL1_SET - mov_q tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ + mov_q tcr, TCR_TxSZ(VA_BITS_MIN) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS tcr_clear_errata_bits tcr, x9, x5 -#ifdef CONFIG_ARM64_VA_BITS_52 - sub x9, xzr, x0 - add x9, x9, #64 - tcr_set_t1sz tcr, x9 -#else +#if VA_BITS > VA_BITS_MIN +alternative_if ARM64_HAS_LVA + eor tcr, tcr, #TCR_T1SZ(VA_BITS) ^ TCR_T1SZ(VA_BITS_MIN) +alternative_else_nop_endif +#elif VA_BITS < 48 idmap_get_t0sz x9 -#endif tcr_set_t0sz tcr, x9 +#endif /* * Set the IPS bits in TCR_EL1. diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index f1c0347ec31a85c7..ec650a2cf4330179 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -30,6 +30,7 @@ HAS_GENERIC_AUTH_IMP_DEF HAS_IRQ_PRIO_MASKING HAS_LDAPR HAS_LSE_ATOMICS +HAS_LVA HAS_NO_FPSIMD HAS_NO_HW_PREFETCH HAS_PAN