From patchwork Thu Nov 17 10:31:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Niedermaier X-Patchwork-Id: 13046618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71DF0C43217 for ; Thu, 17 Nov 2022 11:19:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lOKvGjHKPi8xTZYGKGL3g2vvb3NfS7NziWYpYL4Dmvs=; b=ZAuKhOxNHpw2eB wz7Dtqd+VHcXuMFd4JYRIfWdvof7gKU9j8VnfxAjcfzpFDnq/dvfrNjokm1XeCm+uKQo3aYgz6fcn uZR/47SK29nL2fawtLp+LztHh7hSM9uBSr2rDsc18wq7byJJA0k8bX8ROd6YlihkrkPDF8EMUeXrC FwbjVs+aVmHDI00h8WA5Fz83Aa7OalIDXdYsVFjgdfbYfpHCAUWMTNW1wEVoUIeBQyeRS5RXtquSt G1a9labbGlVpsCMlk1VRy41w/gXLxjUrhx3guo1wPPHkZ4QZJvR1hTyWBfRl51TRos090EadIYkxP hhga2yKXvb+MGnJ/R4dA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovcuH-00D5r4-Ci; Thu, 17 Nov 2022 11:18:09 +0000 Received: from mx3.securetransport.de ([2a01:4f8:c0c:92be::1]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovcuD-00D5mS-2i for linux-arm-kernel@lists.infradead.org; Thu, 17 Nov 2022 11:18:07 +0000 Received: from mail.dh-electronics.com (unknown [77.24.89.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx3.securetransport.de (Postfix) with ESMTPSA id 104375DC78; Thu, 17 Nov 2022 12:17:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dh-electronics.com; s=dhelectronicscom; t=1668683863; bh=J9cZwzQE+zz5MbYAX9m29OHNvL0jHGhjwzt+UWImgWQ=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=svxfdq2a5z6WyczBaXNjn7X4S+JXxvs2S30BUMEZXaH+Io6B+y5gbO+bJNRXscd7/ ZKrOXgqUbX7h78GpHPhnC5zMXQVHv9/g7PEZ2KOQqToq1XEECS40hh2lDnyefcewY7 sz7vkamX5qhihrwGCIIPZc/i0g+3Rv2bjKYjO3TuGNHym6JxoJykhYxZfptNnGYFjy eQSBr+nVNcLNJDgra2JoNu/ak6b3QMuj1vDkQfvPEhyDKmL04x2nDaOouJ1B14UfK8 n9EtLQMV66kWUSoK59oTh1ksQToTQvrQWKFTb49rQ3iF9Tv38yPdkBlk0/VA4LCmdl 9h6B2s+JwYqYQ== Received: from DHPWEX01.DH-ELECTRONICS.ORG (10.64.2.30) by DHPWEX01.DH-ELECTRONICS.ORG (10.64.2.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.20; Thu, 17 Nov 2022 11:32:35 +0100 Received: from Stretch-CN.dh-electronics.org (10.64.6.116) by DHPWEX01.DH-ELECTRONICS.ORG (10.64.2.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.20 via Frontend Transport; Thu, 17 Nov 2022 11:32:35 +0100 From: Christoph Niedermaier To: CC: Christoph Niedermaier , Rob Herring , Krzysztof Kozlowski , Peng Fan , Shawn Guo , Marek Vasut , Fabio Estevam , NXP Linux Team , Subject: [PATCH 4/4] ARM: dts: imx6ull-dhcom: Add DHSOM based DRC02 board Date: Thu, 17 Nov 2022 11:31:34 +0100 Message-ID: <20221117103134.6452-5-cniedermaier@dh-electronics.com> X-Mailer: git-send-email 2.11.0 X-klartext: yes In-Reply-To: <20221117103134.6452-1-cniedermaier@dh-electronics.com> References: <20221117103134.6452-1-cniedermaier@dh-electronics.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221117_031805_468733_8F6E120E X-CRM114-Status: GOOD ( 20.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DT for DH DRC02 unit, which is a universal controller device. The system has two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. For this board a DHCOM i.MX6ULL SoM configuration without WiFi/BT is used. The interface is used for the SD card instead. Signed-off-by: Christoph Niedermaier --- Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Peng Fan Cc: Shawn Guo Cc: Marek Vasut Cc: Fabio Estevam Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ull-dhcom-drc02.dts | 144 ++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9ae8af0c1459..81ecaa32df07 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -739,6 +739,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-colibri-wifi-eval-v3.dtb \ imx6ull-colibri-wifi-iris.dtb \ imx6ull-colibri-wifi-iris-v2.dtb \ + imx6ull-dhcom-drc02.dtb \ imx6ull-dhcom-pdk2.dtb \ imx6ull-dhcom-picoitx.dtb \ imx6ull-jozacp.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts new file mode 100644 index 000000000000..268e4de6be7d --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * DRC02 PCB number: 568-100 or newer (2nd ethernet by internal USB device) + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" +#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on DRC02"; + compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; +}; + +/* + * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. + * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1 + * node below. + */ +&can2 { + status = "okay"; +}; + +&fec1 { + phy-handle = <&mdio1_phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mdio1_phy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; + pinctrl-names = "default"; + reg = <0>; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + }; +}; + +/* Disabled, because 2nd ethernet is provided by an internal USB device */ +&fec2 { + status = "disabled"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "DRC02-In2", + "", "", "", "", + "", "", "DHCOM-I", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "DRC02-HW0", "DRC02-HW1", "DHCOM-M", + "DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6ULL UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <25 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2", + "DHCOM-E", "", "", "DRC02-Out1", + "DRC02-In1", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { /* DHCOM I2C2 */ + eeprom@56 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x56>; + }; +}; + +&uart1 { + /delete-property/ uart-has-rtscts; + rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ + cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */ +}; + +&uart2 { /* Use UART as RS485 */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + >; + }; +};