From patchwork Thu Nov 17 13:24:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13046885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFFCBC4332F for ; Thu, 17 Nov 2022 13:26:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r/fIBnepGq67RMMvHP9nma7CbudqZD+sXpiDGqhIoIw=; b=Ocbzvr+L9pH0Yl ba+vlykR2VTyjPiuARFU5NPpanaaPyWiFe0wjo/3oXq3veUx5O6m5QLm+0iHdYQDnyHy3J2BFyUq7 WlBYtJCEi5eG8hz9wEnEjOl4Sx9f98cxlCdIQ+8Z/HwvukFUXht6u659u/+ZFiliIro0XMyQy13i/ tYvsO70VRv5v8vfVTxd0YmODrhhjQiyNIK0HcIWvhDYNUX38CYZ3gicUr97KNbeP2uSvsBhO7OPPw FXNd92x+wIYFmQ6ODybHf8XFTXnIJ+f7MNrh1ZV+sYdIjGyLazeZO4Jb05QXYRkf1XbKEPo0ytXv3 gjul+/r92lXAPtIiEijQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovetl-00EFKY-S4; Thu, 17 Nov 2022 13:25:45 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovese-00EELC-6e for linux-arm-kernel@lists.infradead.org; Thu, 17 Nov 2022 13:24:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 74CF561E12; Thu, 17 Nov 2022 13:24:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C393CC43147; Thu, 17 Nov 2022 13:24:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668691474; bh=pkN5Mwyz2eezDoSj/Bp9rGtwwycTPyvCRefUHMOLCd0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=To1Ob654V5RLFyDEf/i5NWc+bCZkcMCJ8OGT/U80xlOLGDzkmJ/mrCNUcQjsc8Cyh uW0nBTlJSbKgx6KWbv686GAGUe4ptadt4zA6WioCFpRwCm4sILgiC6KCZVsmS2lj2f j3ZIgqt2VIhyDgIba+SMDFCEoxXS5udcoBc1jRlOxOQJHqxfIMpMK3y2sxpBMNtDcf 1eg9fbpWhplS8k/rzNje/ybEq1V0dHyC6Np6uthfMOu5sCBVeDSb3FLXiLTZRc3+y7 j8A+Ah3H28yADbtxODbbg7dLqkE6QgQqDSGvTsLuR9fP705mFSMomHq3DDVK9F99IH UySV+389Vzp0w== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Marc Zyngier , Will Deacon , Mark Rutland , Kees Cook , Catalin Marinas , Mark Brown , Anshuman Khandual , Richard Henderson Subject: [RFC PATCH 2/7] arm64: mm: Disable all 52-bit virtual addressing support with arm64.nolva Date: Thu, 17 Nov 2022 14:24:18 +0100 Message-Id: <20221117132423.1252942-3-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221117132423.1252942-1-ardb@kernel.org> References: <20221117132423.1252942-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4476; i=ardb@kernel.org; h=from:subject; bh=pkN5Mwyz2eezDoSj/Bp9rGtwwycTPyvCRefUHMOLCd0=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBjdjX+Of0NfaR83yimKuNPD+dyor1wEMxyV1gk8lE6 vCyqaiWJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCY3Y1/gAKCRDDTyI5ktmPJHlaC/ 9hJ0W6Mv33zZXQuI4I4SPAZbbPczlcSqm6QgIMasbpBa8BpGFrVXYLowcT5Zbqe1jpl+PTSd6pNFH5 qnVd2ujjRYCZ1rcV6n+yRfU2EApE/BWm3BSzObGf9EOJa37x1AaFDjWS6o2NLldoSfwrA55UxWsBC2 8pGmIUKukE1Lkym9Jr0wxml1Wf4TI87SGYRCo//A0Um4aZcbWWMXbh2LfmSVK6A7fTVheXpNm9hpiU q8CyeEMspXKuG1M+V9jPWIunmeTnUOurT1BDAv3sx0rmj5SWcl6VnUNlWnRi+4O3GA1NqZX3J9qEvs EhfPDW/zl3KJzTuX9WHcg2UEtl7JvF5Hp9kJ+628u72QtEuGMZcG4D1lOpFUuBQ4+iPv3ZbuhT3M/w RXll2nS5QnZGCNiuI9QspyWFDXPtu5+FSG/mEfRKbkmsJ/7YUTAeV2PLYpc2IyjlhDMbph8Zcsskw4 3RACHJ69bL1WN6gdLU8POr2SmgJO1SVIW27mDvtK6ZGok= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221117_052436_389323_FFCE6B75 X-CRM114-Status: GOOD ( 15.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The LVA feature only applies to 64k pages configurations, and for smaller page sizes there are other feature registers that describe the virtual addressing capabilities of the CPU. Let's adhere to the principle of least surprise, and wire up arm64.nolva so that it disables 52-bit virtual addressing support regardless of the page size. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/kernel/cpufeature.c | 4 ++- arch/arm64/kernel/image-vars.h | 1 + arch/arm64/kernel/pi/idreg-override.c | 26 ++++++++++++++++++++ 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 7aa9cd4fc67f7c61..dbf0186f46ae54ef 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -910,6 +910,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1) struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id); +extern struct arm64_ftr_override id_aa64mmfr0_override; extern struct arm64_ftr_override id_aa64mmfr1_override; extern struct arm64_ftr_override id_aa64mmfr2_override; extern struct arm64_ftr_override id_aa64pfr0_override; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 469d8b31487e88b6..4a631a6e7e42b981 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -636,6 +636,7 @@ static const struct arm64_ftr_bits ftr_raz[] = { #define ARM64_FTR_REG(id, table) \ __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) +struct arm64_ftr_override id_aa64mmfr0_override; struct arm64_ftr_override id_aa64mmfr1_override; struct arm64_ftr_override id_aa64mmfr2_override; struct arm64_ftr_override id_aa64pfr0_override; @@ -701,7 +702,8 @@ static const struct __ftr_reg_entry { &id_aa64isar2_override), /* Op1 = 0, CRn = 0, CRm = 7 */ - ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), + ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, + &id_aa64mmfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, &id_aa64mmfr1_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, diff --git a/arch/arm64/kernel/image-vars.h b/arch/arm64/kernel/image-vars.h index 3bdf0e7865730213..82bafa1f869c3a8b 100644 --- a/arch/arm64/kernel/image-vars.h +++ b/arch/arm64/kernel/image-vars.h @@ -45,6 +45,7 @@ PROVIDE(__pi_memstart_offset_seed = memstart_offset_seed); PROVIDE(__pi_id_aa64isar1_override = id_aa64isar1_override); PROVIDE(__pi_id_aa64isar2_override = id_aa64isar2_override); +PROVIDE(__pi_id_aa64mmfr0_override = id_aa64mmfr0_override); PROVIDE(__pi_id_aa64mmfr1_override = id_aa64mmfr1_override); PROVIDE(__pi_id_aa64mmfr2_override = id_aa64mmfr2_override); PROVIDE(__pi_id_aa64pfr0_override = id_aa64pfr0_override); diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel/pi/idreg-override.c index 3be2f887e6cae29f..aeab2198720ac67c 100644 --- a/arch/arm64/kernel/pi/idreg-override.c +++ b/arch/arm64/kernel/pi/idreg-override.c @@ -139,10 +139,36 @@ DEFINE_OVERRIDE(6, sw_features, "arm64_sw", arm64_sw_feature_override, FIELD("nowxn", ARM64_SW_FEATURE_OVERRIDE_NOWXN), {}); +asmlinkage bool __init mmfr2_varange_filter(u64 val) +{ + u64 mmfr0, tg4, tg16; + + if (val) + return false; + + mmfr0 = read_sysreg(id_aa64mmfr0_el1); + tg4 = (mmfr0 & ID_AA64MMFR0_EL1_TGRAN4_MASK) >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT; + tg16 = (mmfr0 & ID_AA64MMFR0_EL1_TGRAN16_MASK) >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT; + + if (tg4 == ID_AA64MMFR0_EL1_TGRAN4_52_BIT) { + id_aa64mmfr0_override.val |= + ID_AA64MMFR0_EL1_TGRAN4_IMP << ID_AA64MMFR0_EL1_TGRAN4_SHIFT; + id_aa64mmfr0_override.mask |= ID_AA64MMFR0_EL1_TGRAN4_MASK; + } + + if (tg16 == ID_AA64MMFR0_EL1_TGRAN16_52_BIT) { + id_aa64mmfr0_override.val |= + ID_AA64MMFR0_EL1_TGRAN16_IMP << ID_AA64MMFR0_EL1_TGRAN16_SHIFT; + id_aa64mmfr0_override.mask |= ID_AA64MMFR0_EL1_TGRAN16_MASK; + } + return true; +} + DEFINE_OVERRIDE(7, mmfr2, "id_aa64mmfr2", id_aa64mmfr2_override, FIELD("varange", ID_AA64MMFR2_EL1_VARange_SHIFT), FIELD("e0pd", ID_AA64MMFR2_EL1_E0PD_SHIFT), {}); +DEFINE_OVERRIDE_FILTER(mmfr2, 0, mmfr2_varange_filter); /* * regs[] is populated by R_AARCH64_PREL32 directives invisible to the compiler