From patchwork Mon Nov 21 14:39:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 13051176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22397C43217 for ; Mon, 21 Nov 2022 14:45:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Date:MIME-Version:References:Subject:Cc :To:From:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: List-Owner; bh=tuCkNSdoRQsTkZqasO1E+CGtsVb9SSfKx39zhvygX+E=; b=a35tU1SO8y2BAE jsjtvdMZ2GUuTF4fULDr+hsLe0q+9G/VA0IpgJ7vsc7w38L6QMCTRXK/8I5JC52NAw5ImRerk023H eEceoOPMgoFNsc5HK/SHU8Y40emEKDcFuTV57iEFEZqiiWbPhCbBquzJnhc6vX5Koyf04ARRqMGs3 3AXHLvLjRxH4osPhbZFYXFOgJEtI6CrRL2hIqSy3oRiKCrR1qNXN572xfQFbkhsRzGUy/yDUMLx68 jK76I8DBcHvnSbDz79YOF8Gve9uTucPSm8LHKJ4hqwmocDCD4qB3obnc0hUpCNLMcvTMyMuDb1s+e xFz1CYkkrYiTGSSKnqwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ox81Y-00EmHo-T0; Mon, 21 Nov 2022 14:43:53 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ox7xW-00EiL8-PN for linux-arm-kernel@lists.infradead.org; Mon, 21 Nov 2022 14:39:45 +0000 Message-ID: <20221121140048.913023922@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=idBO2Jn3x7lJLQyPZWlY/n45k+pAZ7w1xLsTIR+PA4Q=; b=vYJ3zwSV7ba7WJwns1j0+2RwIgwpv41OLCYeXbqcxPsKW7xxH3hu5JG8a5gekFdSnHDMwk vCEnkFzoW3KSLiz2b5rqXGHcwZbsJuj4WwPpOAOXpDpInmL/LTLAXsV3BFPyPAFDtGzZ6+ V+Z8xHB8vYIdUkG57DCiCeVOf+qFaZK3bKwva4LDpEV73Lvt8cocbRC0PjCtYRYDVdTS8T Rzb3AD2JkOBlqMS8IpMvRlkoI2SQ37mjUPFs5A54cLryF0XFkzumCTRPIHaT18DXI1UaYE nG3WJuzYkhsp9Zwzk9Yka/kC3JZmXzaJxwnZvfbTCdGiYYhK81qp0YTwiJoGbg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=idBO2Jn3x7lJLQyPZWlY/n45k+pAZ7w1xLsTIR+PA4Q=; b=fPTd3YlKMUbpX7p/xnzUnj3Y1k0ggMFVNh1oc6avPGlyM1NCHu7cEj3F77oxLPltSAxWwj HJodJOv7sk1eX8BQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 10/40] irqchip: Provide irq-gic-lib References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:41 +0100 (CET) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221121_063943_144716_1093DE84 X-CRM114-Status: GOOD ( 24.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All irqdomains which provide MSI parent domain functionality for per device MSI domains need to provide a select() callback for the irqdomain and a function to initialize the child domain. Most of these functions would just be copy&pasta with minimal modifications, so provide a library function which implements the required functionality and is customizable via parent_domain::msi_parent_ops Signed-off-by: Thomas Gleixner --- V2: Export functions for modular irqchip drivers... --- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 drivers/irqchip/irq-gic-msi-lib.c | 112 ++++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-msi-lib.h | 19 ++++++ 4 files changed, 135 insertions(+) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -30,6 +30,9 @@ config ARM_GIC_V2M config GIC_NON_BANKED bool +config ARM_GIC_MSI_LIB + bool + config ARM_GIC_V3 bool select IRQ_DOMAIN_HIERARCHY --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_SPEAR3XX) += spear-sh obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o +obj-$(CONFIG_ARM_GIC_MSI_LIB) += irq-gic-msi-lib.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o --- /dev/null +++ b/drivers/irqchip/irq-gic-msi-lib.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2022 Linutronix GmbH +// Copyright (C) 2022 Intel + +#include + +#include "irq-gic-msi-lib.h" + +/** + * gic_msi_lib_init_dev_msi_info - Domain info setup for MSI domains + * @dev: The device for which the domain is created for + * @domain: The domain providing this callback + * @real_parent: The real parent domain of the to initialize domain + * which might be a domain built on top of @domain + * or @domain itself + * @info: The domain info for the to initialize domain + * + * This function is to be used for all types of MSI domains above the root + * parent domain and any intermediates. The topmost parent domain specific + * functionality is determined via @real_parent. + * + * All intermediate domains between the root and the device domain must + * have either msi_parent_ops.init_dev_msi_info = msi_parent_init_dev_msi_info + * or invoke it down the line. + */ +bool gic_msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info) +{ + const struct msi_parent_ops *pops = real_parent->msi_parent_ops; + + /* + * MSI parent domain specific settings. For now there is only the + * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is + * possible to stack MSI parents. See x86 vector -> irq remapping + */ + if (domain->bus_token == pops->bus_select_token) { + if (WARN_ON_ONCE(domain != real_parent)) + return false; + } else { + WARN_ON_ONCE(1); + return false; + } + + /* Parent ops available? */ + if (WARN_ON_ONCE(!pops)) + return false; + + /* Is the target domain bus token supported ? */ + switch(info->bus_token) { + default: + /* + * This should never be reached. See + * gic_msi_lib_irq_domain_select() + */ + WARN_ON_ONCE(1); + return false; + } + + /* + * Mask out the domain specific MSI feature flags which are not + * supported by the real parent. + */ + info->flags &= pops->supported_flags; + /* Enforce the required flags */ + info->flags |= pops->required_flags; + + /* Chip updates for all child bus types */ + if (!info->chip->irq_eoi) + info->chip->irq_eoi = irq_chip_eoi_parent; + + /* + * The device MSI domain can never have a set affinity callback it + * always has to rely on the parent domain to handle affinity + * settings. The device MSI domain just has to write the resulting + * MSI message into the hardware which is the whole purpose of the + * device MSI domain aside of mask/unmask which is provided e.g. by + * PCI/MSI device domains. + */ + info->chip->irq_set_affinity = msi_domain_set_affinity; + return true; +} +EXPORT_SYMBOL_GPL(gic_msi_lib_init_dev_msi_info); + +/** + * gic_msi_lib_irq_domain_select - Shared select function for NEXUS domains + * @d: Pointer to the irq domain on which select is invoked + * @fwspec: Firmware spec describing what is searched + * @bus_token: The bus token for which a matching irq domain is looked up + * + * Returns: %0 if @d is not what is being looked for + * + * %1 if @d is either the domain which is directly searched for or + * if @d is providing the parent MSI domain for the functionality + * requested with @bus_token. + */ +int gic_msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + const struct msi_parent_ops *ops = d->msi_parent_ops; + u32 busmask = BIT(bus_token); + + if (fwspec->fwnode != d->fwnode || fwspec->param_count != 0) + return 0; + + /* Handle pure domain searches */ + if (bus_token == ops->bus_select_token) + return 1; + + return ops && !!(ops->bus_select_mask & busmask); +} +EXPORT_SYMBOL_GPL(gic_msi_lib_irq_domain_select); --- /dev/null +++ b/drivers/irqchip/irq-gic-msi-lib.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2022 Linutronix GmbH +// Copyright (C) 2022 Intel + +#ifndef _DRIVERS_IRQCHIP_IRQ_GIC_MSI_LIB_H +#define _DRIVERS_IRQCHIP_IRQ_GIC_MSI_LIB_H + +#include +#include +#include + +int gic_msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token); + +bool gic_msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info); + +#endif /* _DRIVERS_IRQCHIP_IRQ_GIC_MSI_LIB_H */