Message ID | 20221124102745.2620370-4-sarath.babu.naidu.gaddam@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Xilinx DMA enhancements and optimization | expand |
On 24-11-22, 15:57, Sarath Babu Naidu Gaddam wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > > Read DT property to check if AXI DMA is connected to streaming IP > i.e axiethernet. If connected pass AXI4-Stream control words to > dma client using metadata_ops dmaengine API. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > drivers/dma/xilinx/xilinx_dma.c | 37 +++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 8cd4e69dc7b4..f783ba86cb09 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -493,6 +493,7 @@ struct xilinx_dma_config { > * @s2mm_chan_id: DMA s2mm channel identifier > * @mm2s_chan_id: DMA mm2s channel identifier > * @max_buffer_len: Max buffer length > + * @has_axistream_connected: AXI DMA connected to AXI Stream IP > */ > struct xilinx_dma_device { > void __iomem *regs; > @@ -511,6 +512,7 @@ struct xilinx_dma_device { > u32 s2mm_chan_id; > u32 mm2s_chan_id; > u32 max_buffer_len; > + bool has_axistream_connected; > }; > > /* Macros */ > @@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, > } > } > > +/** > + * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length > + * @tx: async transaction descriptor > + * @payload_len: metadata payload length > + * @max_len: metadata max length > + * Return: The app field pointer. > + */ > +static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, > + size_t *payload_len, size_t *max_len) > +{ > + struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); > + struct xilinx_axidma_tx_segment *seg; > + > + *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; > + seg = list_first_entry(&desc->segments, > + struct xilinx_axidma_tx_segment, node); > + return seg->hw.app; > +} > + > +static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { > + .get_ptr = xilinx_dma_get_metadata_ptr, > +}; > + > /* ----------------------------------------------------------------------------- > * Descriptors and segments alloc and free > */ > @@ -2219,6 +2244,9 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( > segment->hw.control |= XILINX_DMA_BD_EOP; > } > > + if (chan->xdev->has_axistream_connected) > + desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; This is an optional property which is added now, what will happen if you are on a system with older DT? This wont work there.. > + > return &desc->async_tx; > > error: > @@ -3065,6 +3093,11 @@ static int xilinx_dma_probe(struct platform_device *pdev) > } > } > > + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { > + xdev->has_axistream_connected = > + of_property_read_bool(node, "xlnx,axistream-connected"); > + } > + > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > err = of_property_read_u32(node, "xlnx,num-fstores", > &num_frames); > @@ -3090,6 +3123,10 @@ static int xilinx_dma_probe(struct platform_device *pdev) > else > xdev->ext_addr = false; > > + /* Set metadata mode */ > + if (xdev->has_axistream_connected) > + xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; > + > /* Set the dma mask bits */ > err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); > if (err < 0) { > -- > 2.25.1
> -----Original Message----- > From: Vinod Koul <vkoul@kernel.org> > Sent: Wednesday, December 28, 2022 4:30 PM > To: Gaddam, Sarath Babu Naidu > <sarath.babu.naidu.gaddam@amd.com> > Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > lars@metafoo.de; adrianml@alumnos.upm.es; > dmaengine@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Simek, Michal > <michal.simek@amd.com>; Pandey, Radhey Shyam > <radhey.shyam.pandey@amd.com>; Sarangi, Anirudha > <anirudha.sarangi@amd.com>; Katakam, Harini > <harini.katakam@amd.com>; git (AMD-Xilinx) <git@amd.com> > Subject: Re: [PATCH V2 3/6] dmaengine: xilinx_dma: Pass AXI4-Stream > control words to dma client > > On 24-11-22, 15:57, Sarath Babu Naidu Gaddam wrote: > > From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > > > > Read DT property to check if AXI DMA is connected to streaming IP i.e > > axiethernet. If connected pass AXI4-Stream control words to dma client > > using metadata_ops dmaengine API. > > > > Signed-off-by: Radhey Shyam Pandey > <radhey.shyam.pandey@xilinx.com> > > --- > > drivers/dma/xilinx/xilinx_dma.c | 37 > > +++++++++++++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > > b/drivers/dma/xilinx/xilinx_dma.c index 8cd4e69dc7b4..f783ba86cb09 > > 100644 > > --- a/drivers/dma/xilinx/xilinx_dma.c > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > @@ -493,6 +493,7 @@ struct xilinx_dma_config { > > * @s2mm_chan_id: DMA s2mm channel identifier > > * @mm2s_chan_id: DMA mm2s channel identifier > > * @max_buffer_len: Max buffer length > > + * @has_axistream_connected: AXI DMA connected to AXI Stream IP > > */ > > struct xilinx_dma_device { > > void __iomem *regs; > > @@ -511,6 +512,7 @@ struct xilinx_dma_device { > > u32 s2mm_chan_id; > > u32 mm2s_chan_id; > > u32 max_buffer_len; > > + bool has_axistream_connected; > > }; > > > > /* Macros */ > > @@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct > xilinx_dma_chan *chan, > > } > > } > > > > +/** > > + * xilinx_dma_get_metadata_ptr- Populate metadata pointer and > payload > > +length > > + * @tx: async transaction descriptor > > + * @payload_len: metadata payload length > > + * @max_len: metadata max length > > + * Return: The app field pointer. > > + */ > > +static void *xilinx_dma_get_metadata_ptr(struct > dma_async_tx_descriptor *tx, > > + size_t *payload_len, size_t > *max_len) { > > + struct xilinx_dma_tx_descriptor *desc = > to_dma_tx_descriptor(tx); > > + struct xilinx_axidma_tx_segment *seg; > > + > > + *max_len = *payload_len = sizeof(u32) * > XILINX_DMA_NUM_APP_WORDS; > > + seg = list_first_entry(&desc->segments, > > + struct xilinx_axidma_tx_segment, node); > > + return seg->hw.app; > > +} > > + > > +static struct dma_descriptor_metadata_ops > xilinx_dma_metadata_ops = { > > + .get_ptr = xilinx_dma_get_metadata_ptr, }; > > + > > /* ----------------------------------------------------------------------------- > > * Descriptors and segments alloc and free > > */ > > @@ -2219,6 +2244,9 @@ static struct dma_async_tx_descriptor > *xilinx_dma_prep_slave_sg( > > segment->hw.control |= XILINX_DMA_BD_EOP; > > } > > > > + if (chan->xdev->has_axistream_connected) > > + desc->async_tx.metadata_ops = > &xilinx_dma_metadata_ops; > > This is an optional property which is added now, what will happen if you > are on a system with older DT? This wont work there.. Sorry, we missed this comment. If this optional property is not there, then driver does not export "metadata_ops" APIs and it does not break any existing functionality. Thanks, Sarath > > > + > > return &desc->async_tx; > > > > error: > > @@ -3065,6 +3093,11 @@ static int xilinx_dma_probe(struct > platform_device *pdev) > > } > > } > > > > + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { > > + xdev->has_axistream_connected = > > + of_property_read_bool(node, "xlnx,axistream- > connected"); > > + } > > + > > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > > err = of_property_read_u32(node, "xlnx,num-fstores", > > &num_frames); > > @@ -3090,6 +3123,10 @@ static int xilinx_dma_probe(struct > platform_device *pdev) > > else > > xdev->ext_addr = false; > > > > + /* Set metadata mode */ > > + if (xdev->has_axistream_connected) > > + xdev->common.desc_metadata_modes = > DESC_METADATA_ENGINE; > > + > > /* Set the dma mask bits */ > > err = dma_set_mask_and_coherent(xdev->dev, > DMA_BIT_MASK(addr_width)); > > if (err < 0) { > > -- > > 2.25.1 > > -- > ~Vinod
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 8cd4e69dc7b4..f783ba86cb09 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -493,6 +493,7 @@ struct xilinx_dma_config { * @s2mm_chan_id: DMA s2mm channel identifier * @mm2s_chan_id: DMA mm2s channel identifier * @max_buffer_len: Max buffer length + * @has_axistream_connected: AXI DMA connected to AXI Stream IP */ struct xilinx_dma_device { void __iomem *regs; @@ -511,6 +512,7 @@ struct xilinx_dma_device { u32 s2mm_chan_id; u32 mm2s_chan_id; u32 max_buffer_len; + bool has_axistream_connected; }; /* Macros */ @@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, } } +/** + * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length + * @tx: async transaction descriptor + * @payload_len: metadata payload length + * @max_len: metadata max length + * Return: The app field pointer. + */ +static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, + size_t *payload_len, size_t *max_len) +{ + struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); + struct xilinx_axidma_tx_segment *seg; + + *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; + seg = list_first_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + return seg->hw.app; +} + +static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { + .get_ptr = xilinx_dma_get_metadata_ptr, +}; + /* ----------------------------------------------------------------------------- * Descriptors and segments alloc and free */ @@ -2219,6 +2244,9 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( segment->hw.control |= XILINX_DMA_BD_EOP; } + if (chan->xdev->has_axistream_connected) + desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; + return &desc->async_tx; error: @@ -3065,6 +3093,11 @@ static int xilinx_dma_probe(struct platform_device *pdev) } } + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { + xdev->has_axistream_connected = + of_property_read_bool(node, "xlnx,axistream-connected"); + } + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores", &num_frames); @@ -3090,6 +3123,10 @@ static int xilinx_dma_probe(struct platform_device *pdev) else xdev->ext_addr = false; + /* Set metadata mode */ + if (xdev->has_axistream_connected) + xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; + /* Set the dma mask bits */ err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); if (err < 0) {