From patchwork Tue Nov 29 16:14:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13058807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66457C4167B for ; Tue, 29 Nov 2022 16:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eeanUDOjs8VkD3ps3k+PAlgu1lyKwfKh7ShmuRRfVEU=; b=J1bV7IsEITQDaQ PRAsZiA8ifoAO5/JjWqTZZVqzP01L3TERqVh+b4Te80z+34vwA9HhsioLcJVJeCEZo4d6XjRJkcSm PXj8R0SIUIMYirgmao885UjrbgiNb5yimMQ339fNy3rZtm6yj7+4YmlWVPlM8JTwmuaQzKpbVgdgp AeNYYEg5CEZcv6i/s8KEgQnppJ0TfsYqbaIZSqnr6NZxpHhKck9LkWq1UIwbxX2HYVGVHxKpzoqBk EfDJVk3aR0lwhdcm8kGDmvjX+NQnOo3sXmrVUddO4wn8dmLhSfX33izwSttwVgCYpE59ccXyIJumu OJehDbVLuHLTuHGH9yKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p03JG-00A1qk-K2; Tue, 29 Nov 2022 16:18:14 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p03Fj-00A0Zo-7s for linux-arm-kernel@lists.infradead.org; Tue, 29 Nov 2022 16:14:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D6260B811B8; Tue, 29 Nov 2022 16:14:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52030C43470; Tue, 29 Nov 2022 16:14:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669738472; bh=5l50LH5mY6IjiFbDKQ8jAuQAm4lxLhhHcFErsGJlabU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gbFpQtGCfes+aGnPm5KDXi5IlIBLGf0W2bv0EkJ+8czT8T4IcpSjkJd/slIQ4nwfx bYnkPN8ayGAzECt0rPTDARR6xk4A39wQhlTwa7HjgBxlPWXbxJ01EyvFfrUIFEQi6W JcCp3PiQKrY4NDv3WQSskOZef8R5r1zIgat9BxfU2nFw/uEtbHJXowmNFzU8sLKZrx /nWu0KHZOIoU9SojiwJ8Lqlf/CuaXU8FMO+RJ4lg0w/iHEh8m/CxDjnLUSzcgSW+B9 OH1RaUGthJay12q8n96ryNG1aTswR62cJyjs7Dvzw2dtLhaLsgYQ3THlyCzU00QwS8 SjRYs2EuJhvUQ== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Will Deacon , Catalin Marinas , Marc Zyngier , Mark Rutland Subject: [PATCH v6 5/6] arm64: head: Clean the ID map and the HYP text to the PoC if needed Date: Tue, 29 Nov 2022 17:14:17 +0100 Message-Id: <20221129161418.1968319-6-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221129161418.1968319-1-ardb@kernel.org> References: <20221129161418.1968319-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3817; i=ardb@kernel.org; h=from:subject; bh=5l50LH5mY6IjiFbDKQ8jAuQAm4lxLhhHcFErsGJlabU=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBjhi/Xn/Wlo7Yh6xIAq3GD8OYXYy11cMzpkaYHdSng QB5bBmqJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCY4Yv1wAKCRDDTyI5ktmPJGYrC/ 9Go7veaYjzF+RA81LrzU0K7rxkAkJmTlM/6AOvRqfMTiCl+lz0XvgYhG1JmHZEnJcZEXhiErn8FPYd FO+TNqngrciW5NPS6jWsGH8TV36UWekk3EFlcDbmYdSCjLHSnju0WTeLjeu0dHsvSLfnuRDzZjozlO nplXaU+a7CcnSTuF0QKWuwNvmP/yok3kc0lSC7swvyH0jpfKbXn+RgPocjNQBdvIJU02/k4Q7TN+m7 vrmKeD9NzQwaLV3jyKH4QcFAuF/kFHB3CyWtxBLDfcGZU2xV+XfI7V0yP9Ga13tBckXAN0OA3NP6xm eaWp0UR0Q/WP8/nSbG2XeoqkFOAPsCrVWQSYSE255VXJKyNOJSGozLQ9FQZfWVPfFh+jPbyBfa/QR+ r48l0bxX7Cb6g+YoPzPZlhA1Cr/dnQemq4uXAj76e1/ibcmTNbn50E9MAtcMOFcL9x6VS3dx2JYAwA TAf4YYP78QDVMYBe3TALFanjEtWIRr9Q8CQoflQ2YYtCI= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_081435_620368_AACEF44B X-CRM114-Status: GOOD ( 18.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If we enter with the MMU and caches enabled, the bootloader may not have performed any cache maintenance to the PoC. So clean the ID mapped page to the PoC, to ensure that instruction and data accesses with the MMU off see the correct data. For similar reasons, clean all the HYP text to the PoC as well when entering at EL2 with the MMU and caches enabled. Note that this means primary_entry() itself needs to be moved into the ID map as well, as we will return from init_kernel_el() with the MMU and caches off. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 30 ++++++++++++++++++-- arch/arm64/kernel/sleep.S | 1 + 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 5abf8f9fdd97b673..d7b908c26253f7fe 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -90,10 +90,22 @@ SYM_CODE_START(efi_primary_entry) bl record_mmu_state b 0f + .section ".idmap.text","awx" SYM_INNER_LABEL(primary_entry, SYM_L_LOCAL) mov x19, xzr // MMU must be off on bare metal boot 0: bl preserve_boot_args bl create_idmap + + /* + * If we entered with the MMU and caches on, clean the ID mapped part + * of the primary boot code to the PoC so we can safely execute it with + * the MMU off. + */ + cbz x19, 1f + adrp x0, __idmap_text_start + adr_l x1, __idmap_text_end + bl dcache_clean_poc +1: mov x0, x19 bl init_kernel_el // w0=cpu_boot_mode mov x20, x0 @@ -115,6 +127,7 @@ SYM_INNER_LABEL(primary_entry, SYM_L_LOCAL) b __primary_switch SYM_CODE_END(primary_entry) + __INIT SYM_CODE_START_LOCAL(record_mmu_state) mrs x19, CurrentEL cmp x19, #CurrentEL_EL2 @@ -511,10 +524,12 @@ SYM_FUNC_END(__primary_switched) * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if * booted in EL1 or EL2 respectively, with the top 32 bits containing * potential context flags. These flags are *not* stored in __boot_cpu_mode. + * + * x0: whether we are being called from the primary boot path with the MMU on */ SYM_FUNC_START(init_kernel_el) - mrs x0, CurrentEL - cmp x0, #CurrentEL_EL2 + mrs x1, CurrentEL + cmp x1, #CurrentEL_EL2 b.eq init_el2 SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) @@ -529,6 +544,14 @@ SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) eret SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) + msr elr_el2, lr + + // clean all HYP code to the PoC if we booted at EL2 with the MMU on + cbz x0, 0f + adrp x0, __hyp_idmap_text_start + adr_l x1, __hyp_text_end + bl dcache_clean_poc +0: mov_q x0, HCR_HOST_NVHE_FLAGS msr hcr_el2, x0 isb @@ -562,7 +585,6 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) msr sctlr_el1, x1 mov x2, xzr 2: - msr elr_el2, lr mov w0, #BOOT_CPU_MODE_EL2 orr x0, x0, x2 eret @@ -573,6 +595,7 @@ SYM_FUNC_END(init_kernel_el) * cores are held until we're ready for them to initialise. */ SYM_FUNC_START(secondary_holding_pen) + mov x0, xzr bl init_kernel_el // w0=cpu_boot_mode mrs x2, mpidr_el1 mov_q x1, MPIDR_HWID_BITMASK @@ -590,6 +613,7 @@ SYM_FUNC_END(secondary_holding_pen) * be used where CPUs are brought online dynamically by the kernel. */ SYM_FUNC_START(secondary_entry) + mov x0, xzr bl init_kernel_el // w0=cpu_boot_mode b secondary_startup SYM_FUNC_END(secondary_entry) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index 7b7c56e048346e97..2ae7cff1953aaf87 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -99,6 +99,7 @@ SYM_FUNC_END(__cpu_suspend_enter) .pushsection ".idmap.text", "awx" SYM_CODE_START(cpu_resume) + mov x0, xzr bl init_kernel_el mov x19, x0 // preserve boot mode #if VA_BITS > 48