From patchwork Wed Nov 30 17:16:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13060155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E006C4321E for ; Wed, 30 Nov 2022 17:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rAKAhBlyV5ksuvu1y8hcHHgrC48xgnJxxXJsfAUbABk=; b=LjCB/kg2Cste4M fFnkKZ4lGbYFWss8GxwraFXtBdNyBNe/86Q7U4hMKAQFxromAvJuWFW6+rDpcx63RyGLMsNFxy0gg TEADB/VHl+31GyQd1pO0BEcU7CQCruL620J5vAmc8+T+s8okWonQZdEWBPWA3GH580ahQmqKfi/bK E1boSjkWIh5xuZ8bYX4YCuAsm/h/UP8MEP6LFKdmRNZ7ZQE7cSrj1oY8o+DVRQhpylTl7kg+skgkr kuJsQrXx2TpRlED6nXkFOjopR0fGxQZCpkID2aD2RjHo2VU9cqmRDyV+x9j3wpVYujIHu1802beAs sMRHvIPcm+uWB4mAuZfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0R1R-0014ex-UU; Wed, 30 Nov 2022 17:37:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0QmV-000xKF-D6 for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 17:22:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A144DD6E; Wed, 30 Nov 2022 09:22:05 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 454933F73B; Wed, 30 Nov 2022 09:21:58 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH v2 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation Date: Wed, 30 Nov 2022 17:16:20 +0000 Message-Id: <20221130171637.718182-22-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221130171637.718182-1-james.morse@arm.com> References: <20221130171637.718182-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_092159_545849_981A52C8 X-CRM114-Status: UNSURE ( 9.08 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_MMFR4_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 10 --------- arch/arm64/tools/sysreg | 38 +++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index be4015d22a30..b9fdb1e0a451 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -171,7 +171,6 @@ #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) @@ -727,15 +726,6 @@ #define ID_ISAR6_EL1_DP_SHIFT 4 #define ID_ISAR6_EL1_JSCVT_SHIFT 0 -#define ID_MMFR4_EL1_EVT_SHIFT 28 -#define ID_MMFR4_EL1_CCIDX_SHIFT 24 -#define ID_MMFR4_EL1_LSM_SHIFT 20 -#define ID_MMFR4_EL1_HPDS_SHIFT 16 -#define ID_MMFR4_EL1_CnP_SHIFT 12 -#define ID_MMFR4_EL1_XNX_SHIFT 8 -#define ID_MMFR4_EL1_AC2_SHIFT 4 -#define ID_MMFR4_EL1_SpecSEI_SHIFT 0 - #define ID_MMFR5_EL1_ETS_SHIFT 0 #define ID_PFR0_EL1_DIT_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7573312ef249..7cd258ee7a0f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -223,6 +223,44 @@ Enum 3:0 CMaintVA EndEnum EndSysreg +Sysreg ID_MMFR4_EL1 3 0 0 2 6 +Res0 63:32 +Enum 31:28 EVT + 0b0000 NI + 0b0001 NO_TLBIS + 0b0010 TLBIS +EndEnum +Enum 27:24 CCIDX + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 LSM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 HPDS + 0b0000 NI + 0b0001 AA32HPD + 0b0010 HPDS2 +EndEnum +Enum 15:12 CnP + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 XNX + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 AC2 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 SpecSEI + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64PFR0_EL1 3 0 0 4 0 Enum 63:60 CSV3 0b0000 NI