From patchwork Wed Nov 30 17:16:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13060160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14830C4321E for ; Wed, 30 Nov 2022 17:42:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dCNXpcpJJXaz2N+/FPH2f7ZI66QxAmH12/InMdZ4FvU=; b=ioUpJEDjLs0L6Z /QMLjd/VC/AjYQFR8mFqj5k/8QmP95T11irKQglLL3PaHZTMuEM/us8Ek+SVbvWj1mo90sk0kJVo/ rf7xFRS5G3ERpqgNiC4thypQ74xIUzC3ljYej8lVt/03mYapNk8lCxdqWu9I7swF7j30DSBS+ZevK Y5ogciF1Uhebxy7/5KecfJGwl9pyMxJvVRAi9i5+05O4qiqgU3MGADHxFc9ZFZ/PlHHluPPLP0nT8 LZMRqUwT8WwBpC+tFAVS9m8qFLsimrahYn48Fxv/rIgLddzbIDs2+MY7ZgbZQk9byCqADKBE8whEC /K1BnHENMVAOXFTWXYOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0R51-0016Zu-Dw; Wed, 30 Nov 2022 17:41:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0Qma-000xLI-35 for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 17:22:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8F1B8D6E; Wed, 30 Nov 2022 09:22:10 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32FC03F73B; Wed, 30 Nov 2022 09:22:03 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH v2 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation Date: Wed, 30 Nov 2022 17:16:25 +0000 Message-Id: <20221130171637.718182-27-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221130171637.718182-1-james.morse@arm.com> References: <20221130171637.718182-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_092204_213858_515283C4 X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_ISAR4_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 10 --------- arch/arm64/tools/sysreg | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index bfd69abf1bf7..0a63c39407f2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -173,7 +173,6 @@ #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) -#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) @@ -688,15 +687,6 @@ #define ID_DFR0_EL1_PerfMon_PMUv3p4 0x5 #define ID_DFR0_EL1_PerfMon_PMUv3p5 0x6 -#define ID_ISAR4_EL1_SWP_frac_SHIFT 28 -#define ID_ISAR4_EL1_PSR_M_SHIFT 24 -#define ID_ISAR4_EL1_SynchPrim_frac_SHIFT 20 -#define ID_ISAR4_EL1_Barrier_SHIFT 16 -#define ID_ISAR4_EL1_SMC_SHIFT 12 -#define ID_ISAR4_EL1_Writeback_SHIFT 8 -#define ID_ISAR4_EL1_WithShifts_SHIFT 4 -#define ID_ISAR4_EL1_Unpriv_SHIFT 0 - #define ID_DFR1_EL1_MTPMU_SHIFT 0 #define ID_ISAR5_EL1_RDM_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 1e2d5a3b619c..ed88cc1ae2a8 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -382,6 +382,45 @@ Enum 3:0 Saturate EndEnum EndSysreg +Sysreg ID_ISAR4_EL1 3 0 0 2 4 +Res0 63:32 +Enum 31:28 SWP_frac + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 PSR_M + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 SynchPrim_frac + 0b0000 NI + 0b0011 IMP +EndEnum +Enum 19:16 Barrier + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 SMC + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 Writeback + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 WithShifts + 0b0000 NI + 0b0001 LSL3 + 0b0011 LS + 0b0100 REG +EndEnum +Enum 3:0 Unpriv + 0b0000 NI + 0b0001 REG_BYTE + 0b0010 SIGNED_HALFWORD +EndEnum +EndSysreg + Sysreg ID_MMFR4_EL1 3 0 0 2 6 Res0 63:32 Enum 31:28 EVT