From patchwork Wed Nov 30 17:16:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13060162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB700C433FE for ; Wed, 30 Nov 2022 17:42:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sRZv6aR8rK9PBM7elYxycF3Aid/SEgOtmW4GohQ+KEo=; b=q58rNhAX2ILqbX RoEBoFgEFHzjthGN6aXmqo4neynAt7AfT6iy96NlSG4msHaYQK2BoDzQVfF8RRrnngJ4E6DIgd7me 9HfVMB+LZEI/7R6VQqG+AtBF082ge8L6TctsZS3KgfIqcOgAmOYO8OckecTTp7/usmF+B2b2BcuLH Y6nh2em5Cty3yd554qoy1QLK5ZwuOGHhmyKy69i7LAZYmKHceKd6e8UQzQhtbfWR20cvf0YdsyiQH HcXozFpjZgzS9gAnGRdinwk2pzkiN9RcCeZDY+0igmubky/bVjEGNM60wy4ItsiVAAEYInpfPOP8f a4ng26JzyEDN9eYBQKQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0R5g-0016yK-8z; Wed, 30 Nov 2022 17:41:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0Qmc-000xMH-5w for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 17:22:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8838C1042; Wed, 30 Nov 2022 09:22:12 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C05A3F73B; Wed, 30 Nov 2022 09:22:05 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH v2 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation Date: Wed, 30 Nov 2022 17:16:27 +0000 Message-Id: <20221130171637.718182-29-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221130171637.718182-1-james.morse@arm.com> References: <20221130171637.718182-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_092206_285748_C89D5988 X-CRM114-Status: UNSURE ( 9.25 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_ISAR6_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 10 ---------- arch/arm64/tools/sysreg | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 04a6e44427a9..03f38890cb2b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -173,8 +173,6 @@ #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) -#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) - #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) @@ -688,14 +686,6 @@ #define ID_DFR1_EL1_MTPMU_SHIFT 0 -#define ID_ISAR6_EL1_I8MM_SHIFT 24 -#define ID_ISAR6_EL1_BF16_SHIFT 20 -#define ID_ISAR6_EL1_SPECRES_SHIFT 16 -#define ID_ISAR6_EL1_SB_SHIFT 12 -#define ID_ISAR6_EL1_FHM_SHIFT 8 -#define ID_ISAR6_EL1_DP_SHIFT 4 -#define ID_ISAR6_EL1_JSCVT_SHIFT 0 - #define ID_MMFR5_EL1_ETS_SHIFT 0 #define ID_PFR0_EL1_DIT_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 43e765a2c68f..aa6b3f5316f0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -455,6 +455,38 @@ Enum 3:0 SEVL EndEnum EndSysreg +Sysreg ID_ISAR6_EL1 3 0 0 2 7 +Res0 63:28 +Enum 27:24 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 BF16 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 SPECRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 SB + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 FHM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 DP + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 JSCVT + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_MMFR4_EL1 3 0 0 2 6 Res0 63:32 Enum 31:28 EVT