From patchwork Wed Nov 30 17:16:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13060166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36752C4321E for ; Wed, 30 Nov 2022 17:45:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=obqMZf33rMVVGF8Ht7R51y9s+WYAti3nApJAxYhgDmY=; b=R+z2C97pUI65qX f6QoNfW1hR6n/ySBEzM1njupLI/V+0uhLByUWV4FDYlIH0a2JnyPJUf+bZ3fwu+o/MfLWYkiae2dF CvROx8usQoasE8J2e6Kc7iw00vNYOV2cNbX9EIzB8MkGuc4Fe68Zx6Z1D2VcNYl6hJ2ENl8FNkPYb yOa/7YkaMuGEiOcjONIhM16SbgnoRR5k1vv6jnLZj0RNx23ahGxlfNrV6OtntMXEPngGSFQpGI+wL k62G/X1EiyziHahE4WO3KN7Q/yVkzYLdz/LvgKSFPGjhBNWm+RSzyX45jURRB4MVglsV8xuXL9nnR Mqgi8ZL+Lted9tOmH4mw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0R8Y-0018h9-2S; Wed, 30 Nov 2022 17:44:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0Qme-000xQs-T4 for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 17:22:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 80A771424; Wed, 30 Nov 2022 09:22:14 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 248043F73B; Wed, 30 Nov 2022 09:22:07 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH v2 30/38] arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation Date: Wed, 30 Nov 2022 17:16:29 +0000 Message-Id: <20221130171637.718182-31-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221130171637.718182-1-james.morse@arm.com> References: <20221130171637.718182-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_092209_038025_1BF200C5 X-CRM114-Status: UNSURE ( 8.58 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_PFR1_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 10 --------- arch/arm64/tools/sysreg | 40 +++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 72b32e179b46..85197dd180e0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -165,7 +165,6 @@ #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) -#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) @@ -716,15 +715,6 @@ #define MVFR1_EL1_FPDNaN_SHIFT 4 #define MVFR1_EL1_FPFtZ_SHIFT 0 -#define ID_PFR1_EL1_GIC_SHIFT 28 -#define ID_PFR1_EL1_Virt_frac_SHIFT 24 -#define ID_PFR1_EL1_Sec_frac_SHIFT 20 -#define ID_PFR1_EL1_GenTimer_SHIFT 16 -#define ID_PFR1_EL1_Virtualization_SHIFT 12 -#define ID_PFR1_EL1_MProgMod_SHIFT 8 -#define ID_PFR1_EL1_Security_SHIFT 4 -#define ID_PFR1_EL1_ProgMod_SHIFT 0 - #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 641bd7e3365c..e86193b295e4 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -87,6 +87,46 @@ Enum 3:0 State0 EndEnum EndSysreg +Sysreg ID_PFR1_EL1 3 0 0 1 1 +Res0 63:32 +Enum 31:28 GIC + 0b0000 NI + 0b0001 GICv3 + 0b0010 GICv4p1 +EndEnum +Enum 27:24 Virt_frac + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 Sec_frac + 0b0000 NI + 0b0001 WALK_DISABLE + 0b0010 SECURE_MEMORY +EndEnum +Enum 19:16 GenTimer + 0b0000 NI + 0b0001 IMP + 0b0010 ECV +EndEnum +Enum 15:12 Virtualization + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 MProgMod + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 Security + 0b0000 NI + 0b0001 EL3 + 0b0001 NSACR_RFR +EndEnum +Enum 3:0 ProgMod + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_MMFR0_EL1 3 0 0 1 4 Res0 63:32 Enum 31:28 InnerShr