From patchwork Wed Nov 30 17:16:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13060186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1AEB1C433FE for ; Wed, 30 Nov 2022 17:48:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0Yoe0Rw0r2lxnebtLQFDDJf1oOWAX8oFGUBpFRf8AKw=; b=0gAoxQcpBzH6pP MN5TXR6IVezDyQ90/T/JqIsmNLXioqcQ/j8aRNBxqdt8si4dCTSF4IhFA9C9izBs7fB1H3m2Obfb/ 0MbCgu9fgUN5sZsIQ2y5qc5ifAl4v4X9JdB0PwHtrf27fJcU4dQ+dxn5+hKpIbs2afXkZirSADtaP /lO2GOMu7bJy2ry/Ws/kCkx/Csx58aAL4lRb6IQKayjUs98PvLNRlaELYmDk8cmrhawnBnCvlPlE7 3CslSAkASh8RxmSo/ueZdz6hRfoUPVI/TExKS3NazwfJsLfnRgoYIZJUMItZ06qA2pcQSjho3QG5d ZJpisarT1n5r+492hOgA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0RAq-0019ug-7G; Wed, 30 Nov 2022 17:47:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0Qmh-000xLI-Vz for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 17:22:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 72A4CED1; Wed, 30 Nov 2022 09:22:18 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 168AC3F73B; Wed, 30 Nov 2022 09:22:10 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH v2 34/38] arm64/sysreg: Convert MVFR2_EL1 to automatic generation Date: Wed, 30 Nov 2022 17:16:33 +0000 Message-Id: <20221130171637.718182-35-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221130171637.718182-1-james.morse@arm.com> References: <20221130171637.718182-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_092212_112313_3023471E X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert MVFR2_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Reviewed-by: Mark Brown Signed-off-by: James Morse --- arch/arm64/include/asm/sysreg.h | 5 ----- arch/arm64/tools/sysreg | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d4b787d30fe8..aabc6db300fa 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -170,8 +170,6 @@ #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) -#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) - #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) @@ -708,9 +706,6 @@ #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT #endif -#define MVFR2_EL1_FPMisc_SHIFT 4 -#define MVFR2_EL1_SIMDMisc_SHIFT 0 - #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 3ca7e61265fd..f0481f626405 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -684,6 +684,23 @@ Enum 3:0 FPFtZ EndEnum EndSysreg +Sysreg MVFR2_EL1 3 0 0 3 2 +Res0 63:8 +Enum 7:4 FPMisc + 0b0000 NI + 0b0001 FP + 0b0010 FP_DIRECTED_ROUNDING + 0b0011 FP_ROUNDING + 0b0100 FP_MAX_MIN +EndEnum +Enum 3:0 SIMDMisc + 0b0000 NI + 0b0001 SIMD_DIRECTED_ROUNDING + 0b0010 SIMD_ROUNDING + 0b0011 SIMD_MAX_MIN +EndEnum +EndSysreg + Sysreg ID_PFR2_EL1 3 0 0 3 4 Res0 63:12 Enum 11:8 RAS_frac