From patchwork Wed Nov 30 17:16:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13060189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96AD5C433FE for ; Wed, 30 Nov 2022 17:50:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/wqSPjYItUeyPTaMCYxyLBxHvhvVS53ycept8KAQaa0=; b=e8t/DwhDigvRTz T3q0Aksq6bvxejuURWELTA3RsLJudxGpS/O2RSqWdXBDJ1ROKdJl3l09nkz8dl4TGpo6XFSkmCSnN SDgme9Mc8dvK9PYLS1Z1DLjNaCdYYcQ23zoWmYQ+mUWIl+FpX8X2uxzKk/9Gx+SBk79ZPEFEKXXyU brM2Bp6YSxfRC6YNc75ECgrKNrsis6uLlqIMGHZa7GoBOrXLHlHD0aMVJ+wajIX2j0T5RhR/VFapb A2Z3toAXnxCH5Znz0rRs5qY3PHw2QPiIwrMAvKNm49cmUKBkE0UlZiWh+rT112lkfvqP6ApSZcsgH aKAs9Rfdohc12mjY0moQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0RD3-001BFo-Av; Wed, 30 Nov 2022 17:49:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0Qml-000xUU-PO for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2022 17:22:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 679E11042; Wed, 30 Nov 2022 09:22:21 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0B3233F73B; Wed, 30 Nov 2022 09:22:13 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Mark Brown , Will Deacon , James Morse Subject: [PATCH v2 37/38] arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation Date: Wed, 30 Nov 2022 17:16:36 +0000 Message-Id: <20221130171637.718182-38-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221130171637.718182-1-james.morse@arm.com> References: <20221130171637.718182-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221130_092215_924689_3EB513A1 X-CRM114-Status: UNSURE ( 8.46 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_DFR0_EL1 to be automatically generated as per DDI0487I.a, no functional changes. Signed-off-by: James Morse Reviewed-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 14 --------- arch/arm64/tools/sysreg | 50 +++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index c4d59ea7147a..a20ab575891f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -165,7 +165,6 @@ #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) -#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) @@ -670,21 +669,8 @@ #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 #endif -#define ID_DFR0_EL1_PerfMon_PMUv3 0x3 -#define ID_DFR0_EL1_PerfMon_PMUv3p1 0x4 -#define ID_DFR0_EL1_PerfMon_PMUv3p4 0x5 -#define ID_DFR0_EL1_PerfMon_PMUv3p5 0x6 - #define ID_DFR1_EL1_MTPMU_SHIFT 0 -#define ID_DFR0_EL1_PerfMon_SHIFT 24 -#define ID_DFR0_EL1_MProfDbg_SHIFT 20 -#define ID_DFR0_EL1_MMapTrc_SHIFT 16 -#define ID_DFR0_EL1_CopTrc_SHIFT 12 -#define ID_DFR0_EL1_MMapDbg_SHIFT 8 -#define ID_DFR0_EL1_CopSDbg_SHIFT 4 -#define ID_DFR0_EL1_CopDbg_SHIFT 0 - #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index dd853ce2226d..6ff68bc7e776 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -127,6 +127,56 @@ Enum 3:0 ProgMod EndEnum EndSysreg +Sysreg ID_DFR0_EL1 3 0 0 1 2 +Res0 63:32 +Enum 31:28 TraceFilt + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 PerfMon + 0b0000 NI + 0b0001 PMUv1 + 0b0010 PMUv2 + 0b0011 PMUv3 + 0b0100 PMUv3p1 + 0b0101 PMUv3p4 + 0b0110 PMUv3p5 + 0b0111 PMUv3p7 + 0b1000 PMUv3p8 + 0b1111 IMPDEF +EndEnum +Enum 23:20 MProfDbg + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 MMapTrc + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 CopTrc + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 MMapDbg + 0b0000 NI + 0b0100 Armv7 + 0b0101 Armv7p1 +EndEnum +Field 7:4 CopSDbg +Enum 3:0 CopDbg + 0b0000 NI + 0b0010 Armv6 + 0b0011 Armv6p1 + 0b0100 Armv7 + 0b0101 Armv7p1 + 0b0110 Armv8 + 0b0111 VHE + 0b1000 Debugv8p2 + 0b1001 Debugv8p4 + 0b1010 Debugv8p8 +EndEnum +EndSysreg + Sysreg ID_AFR0_EL1 3 0 0 1 3 Res0 63:16 Field 15:12 IMPDEF3