From patchwork Mon Dec 5 09:49:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chengci.Xu" X-Patchwork-Id: 13064318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB3B9C4321E for ; Mon, 5 Dec 2022 09:53:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=67omTufhzz83+fs6QhBA9t3ubKs6936prarEc5lH0y8=; b=oxhgoLGk6LSGu1 XuOVczxAyqqVQby01LQbkHY5PE9zijIZhD3VFlP0DKcZqCcw6s0VkOyvAEJbv9EhLXGUPj8LIoYBp wAMpm7YszO2QuBlAmRvu7dRMMSnAwSZuutdCwr7FhDC0yBQ5yNlqr3BS1KiGg/0o/KVI4e4xOjdU/ eeE/g05Z6NWY0sMDGzD2xH6fphpGpg68dAJTVlb3HY5b/zlMpmbU59Y2C3LFm65E0ywpDcZTj88uv 4Ul1V/LM7kM15xehcTwCq7v9SDMY3iGvlaSOAiLcV4+GOf16nWubOQi/Vodj0QoaIqWZgp0j9fr+b MzntUk+fwjxjtdyBq7UQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p288s-00HYYV-T5; Mon, 05 Dec 2022 09:52:07 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p288I-00HXdo-Iw; Mon, 05 Dec 2022 09:51:32 +0000 X-UUID: 36c59d034859446383f2d3e3a853ec7a-20221205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oG0KzFFTfRjmNGowXYoHaVod0WVaeGisow3cNxDvyZI=; b=ee9rgDeutRLoD3B3t/VaDS6zLu5+AdYNn8zCajmCPSvz/tgAhPWBOTCVLmW5zGUIFjBHhEOLi505fxkTHxt9BYrO1RHnQFN3bVVkvcE2KFQyhv+3pJArRTLREdbw04F1/2TvFSmW0Cv2LdOMQ4nrQ7uJ1nA+twYb0FNrWZdybag=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:cee06457-6bb2-4765-bbd7-46ae8cc80993,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:a0135824-4387-4253-a41d-4f6f2296b154,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 36c59d034859446383f2d3e3a853ec7a-20221205 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 259526843; Mon, 05 Dec 2022 02:51:22 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 5 Dec 2022 17:50:36 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 5 Dec 2022 17:50:35 +0800 From: Chengci.Xu To: Yong Wu , Joerg Roedel , "Will Deacon" , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Chengci.Xu Subject: [PATCH v5 2/4] iommu/mediatek: Adjust mtk_iommu_config flow Date: Mon, 5 Dec 2022 17:49:59 +0800 Message-ID: <20221205095001.31918-3-chengci.xu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221205095001.31918-1-chengci.xu@mediatek.com> References: <20221205095001.31918-1-chengci.xu@mediatek.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221205_015130_674805_4BE5A086 X-CRM114-Status: GOOD ( 13.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For reduce indention without functional change, prepare for MT8188. If there are many port in a same larb, current flow will update larb_mmu->mmu or update INFRA register for too many times. So we save all port to portid_msk in the front of mtk_iommu_config(), and then update only once for IOMMU configure. By this modification, we can prevent MT8188 from sending to many SMC calls, avoiding enter ATF for each port. Signed-off-by: Chengci.Xu Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 58 +++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5dc1009a19ed..7cf9a9c32fb1 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -545,41 +545,47 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, unsigned int larbid, portid; struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); const struct mtk_iommu_iova_region *region; - u32 peri_mmuen, peri_mmuen_msk; + unsigned long portid_msk = 0; int i, ret = 0; for (i = 0; i < fwspec->num_ids; ++i) { - larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); portid = MTK_M4U_TO_PORT(fwspec->ids[i]); + portid_msk |= BIT(portid); + } - if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { - larb_mmu = &data->larb_imu[larbid]; + if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { + /* All ports should be in the same larb. just use 0 here */ + larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larb_mmu = &data->larb_imu[larbid]; + region = data->plat_data->iova_region + regionid; - region = data->plat_data->iova_region + regionid; + for_each_set_bit(portid, &portid_msk, 32) larb_mmu->bank[portid] = upper_32_bits(region->iova_base); - dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", - enable ? "enable" : "disable", dev_name(larb_mmu->dev), - portid, regionid, larb_mmu->bank[portid]); - - if (enable) - larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); - else - larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); - } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { - peri_mmuen_msk = BIT(portid); - /* PCI dev has only one output id, enable the next writing bit for PCIe */ - if (dev_is_pci(dev)) - peri_mmuen_msk |= BIT(portid + 1); - - peri_mmuen = enable ? peri_mmuen_msk : 0; - ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, - peri_mmuen_msk, peri_mmuen); - if (ret) - dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", - enable ? "enable" : "disable", - dev_name(data->dev), peri_mmuen_msk, ret); + dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n", + enable ? "enable" : "disable", dev_name(larb_mmu->dev), + portid_msk, regionid, upper_32_bits(region->iova_base)); + + if (enable) + larb_mmu->mmu |= portid_msk; + else + larb_mmu->mmu &= ~portid_msk; + } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { + /* PCI dev has only one output id, enable the next writing bit for PCIe */ + if (dev_is_pci(dev)) { + if (fwspec->num_ids != 1) { + dev_err(dev, "PCI dev can only have one port.\n"); + return -ENODEV; + } + portid_msk |= BIT(portid + 1); } + + ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, + (u32)portid_msk, enable ? (u32)portid_msk : 0); + if (ret) + dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n", + enable ? "enable" : "disable", + dev_name(data->dev), portid_msk, ret); } return ret; }