| Message ID | 20221207-arm64-sysreg-helpers-v1-2-149fa1308a23@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64/cpufeature: Make use of sysreg helpers for hwcaps | expand |
On Thu, Dec 08, 2022 at 04:03:23PM +0000, Mark Brown wrote: > The recently converted 32 bit ID registers have errors in MVFR0_EL1.FPSP, > MVFR0_EL1.SIMDReg and MVFR1_EL1.SIMDHP where enumeration values which > should be 0b0010 are specified as 0b0001. Correct these. > > Fixes: e79c94a2a487 ("arm64/sysreg: Convert MVFR0_EL1 to automatic generation") > Fixes: c9b718eda706 ("arm64/sysreg: Convert MVFR1_EL1 to automatic generation") > Signed-off-by: Mark Brown <broonie@kernel.org> These each look like a copy-paste error from the lines immediately above, forgetting to update the value. The updated values as-of this patch appears to be correct per the documentation. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/tools/sysreg | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 184e58fd5631..e8fb6684d7f3 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -689,17 +689,17 @@ EndEnum > Enum 11:8 FPDP > 0b0000 NI > 0b0001 VFPv2 > - 0b0001 VFPv3 > + 0b0010 VFPv3 > EndEnum > Enum 7:4 FPSP > 0b0000 NI > 0b0001 VFPv2 > - 0b0001 VFPv3 > + 0b0010 VFPv3 > EndEnum > Enum 3:0 SIMDReg > 0b0000 NI > 0b0001 IMP_16x64 > - 0b0001 IMP_32x64 > + 0b0010 IMP_32x64 > EndEnum > EndSysreg > > @@ -718,7 +718,7 @@ EndEnum > Enum 23:20 SIMDHP > 0b0000 NI > 0b0001 SIMDHP > - 0b0001 SIMDHP_FLOAT > + 0b0010 SIMDHP_FLOAT > EndEnum > Enum 19:16 SIMDSP > 0b0000 NI > > -- > 2.30.2 > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 184e58fd5631..e8fb6684d7f3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -689,17 +689,17 @@ EndEnum Enum 11:8 FPDP 0b0000 NI 0b0001 VFPv2 - 0b0001 VFPv3 + 0b0010 VFPv3 EndEnum Enum 7:4 FPSP 0b0000 NI 0b0001 VFPv2 - 0b0001 VFPv3 + 0b0010 VFPv3 EndEnum Enum 3:0 SIMDReg 0b0000 NI 0b0001 IMP_16x64 - 0b0001 IMP_32x64 + 0b0010 IMP_32x64 EndEnum EndSysreg @@ -718,7 +718,7 @@ EndEnum Enum 23:20 SIMDHP 0b0000 NI 0b0001 SIMDHP - 0b0001 SIMDHP_FLOAT + 0b0010 SIMDHP_FLOAT EndEnum Enum 19:16 SIMDSP 0b0000 NI
The recently converted 32 bit ID registers have errors in MVFR0_EL1.FPSP, MVFR0_EL1.SIMDReg and MVFR1_EL1.SIMDHP where enumeration values which should be 0b0010 are specified as 0b0001. Correct these. Fixes: e79c94a2a487 ("arm64/sysreg: Convert MVFR0_EL1 to automatic generation") Fixes: c9b718eda706 ("arm64/sysreg: Convert MVFR1_EL1 to automatic generation") Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/tools/sysreg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)