diff mbox series

drm/meson: Reduce the FIFO lines held when AFBC is not used

Message ID 20221216-afbc_s905x-v1-0-033bebf780d9@baylibre.com (mailing list archive)
State New, archived
Headers show
Series drm/meson: Reduce the FIFO lines held when AFBC is not used | expand

Commit Message

Carlo Caione Dec. 19, 2022, 8:43 a.m. UTC 
Having a bigger number of FIFO lines held after vsync is only useful to
SoCs using AFBC to give time to the AFBC decoder to be reset, configured
and enabled again.

For SoCs not using AFBC this, on the contrary, is causing on some
displays issues and a few pixels vertical offset in the displayed image.

Conditionally increase the number of lines held after vsync only for
SoCs using AFBC, leaving the default value for all the others.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
Fix display issues for amlogic SoCs not using AFBC

In 24e0d4058eff the number of lines held after VSYNC was incremented to give
time to the AFBC decoder to do its job. This is causing an issue (seen on
S905x) where the image (on some panels) is dislayed with a vertical offset.
With this patch we try to keep the fix only when AFBC is actually used
filtering on the SoC type.

To: Neil Armstrong <neil.armstrong@linaro.org>
To: David Airlie <airlied@gmail.com>
To: Daniel Vetter <daniel@ffwll.ch>
To: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/gpu/drm/meson/meson_viu.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)


---
base-commit: 84e57d292203a45c96dbcb2e6be9dd80961d981a
change-id: 20221216-afbc_s905x-4baf5fdc9970

Best regards,

Comments

Martin Blumenstingl Dec. 19, 2022, 11 a.m. UTC | #1 
Hi Carlo,

On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
>
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
On the 32-bit SoCs (for which VPU support is not upstream yet) it has
caused screen tearing instead of shifting the image.

> Conditionally increase the number of lines held after vsync only for
> SoCs using AFBC, leaving the default value for all the others.
That was also my approach (for a not-yet-upstream patch).
Since it's affecting already supported SoCs I suggest adding
"Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
is applying the patch).

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Neil Armstrong Dec. 19, 2022, 1:39 p.m. UTC | #2 
On 19/12/2022 12:00, Martin Blumenstingl wrote:
> Hi Carlo,
> 
> On Mon, Dec 19, 2022 at 9:43 AM Carlo Caione <ccaione@baylibre.com> wrote:
>>
>> Having a bigger number of FIFO lines held after vsync is only useful to
>> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
>> and enabled again.
>>
>> For SoCs not using AFBC this, on the contrary, is causing on some
>> displays issues and a few pixels vertical offset in the displayed image.
> On the 32-bit SoCs (for which VPU support is not upstream yet) it has
> caused screen tearing instead of shifting the image.
> 
>> Conditionally increase the number of lines held after vsync only for
>> SoCs using AFBC, leaving the default value for all the others.
> That was also my approach (for a not-yet-upstream patch).
> Since it's affecting already supported SoCs I suggest adding
> "Fixed-by: 24e0d4058eff ..." (maybe Neil can do so when he agrees and
> is applying the patch).
> 
> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>


Yep I'll add the Fixes tag when applying

Thank Carlo !

Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Neil Armstrong Jan. 2, 2023, 10 a.m. UTC | #3 
Hi,

On Mon, 19 Dec 2022 09:43:05 +0100, Carlo Caione wrote:
> Having a bigger number of FIFO lines held after vsync is only useful to
> SoCs using AFBC to give time to the AFBC decoder to be reset, configured
> and enabled again.
> 
> For SoCs not using AFBC this, on the contrary, is causing on some
> displays issues and a few pixels vertical offset in the displayed image.
> 
> [...]

Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git (drm-misc-fixes)

[1/1] drm/meson: Reduce the FIFO lines held when AFBC is not used
      https://cgit.freedesktop.org/drm/drm-misc/commit/?id=3b754ed6d1cd90017e66e5cc16f3923e4a952ffc
diff mbox series

Patch

diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index d4b907889a21..cd399b0b7181 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -436,15 +436,14 @@  void meson_viu_init(struct meson_drm *priv)
 
 	/* Initialize OSD1 fifo control register */
 	reg = VIU_OSD_DDR_PRIORITY_URGENT |
-		VIU_OSD_HOLD_FIFO_LINES(31) |
 		VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
 		VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
 		VIU_OSD_FIFO_LIMITS(2);      /* fifo_lim: 2*16=32 */
 
 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
-		reg |= VIU_OSD_BURST_LENGTH_32;
+		reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
 	else
-		reg |= VIU_OSD_BURST_LENGTH_64;
+		reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
 
 	writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
 	writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));