From patchwork Tue Dec 20 09:29:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhao He X-Patchwork-Id: 13077681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A824C4332F for ; Tue, 20 Dec 2022 09:33:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WVB6qttL3v2X30mwNCE0B6fFufIs4Vjh+5r05SkMMPI=; b=DSXwuvDY+XAAU6 90e9qp1O2YNxpBwJTM+52MXPCWFp34deK/gUErR70Dmwq8JaNt+ew4Kf0sJ/Jpf9U97Odqd5MH/V1 M9F6POlKDUbjQK4SJC4E9sQ7i3TwID5qID1Ze7RwBQLczHK+Ze1/KDrZc0ydjEM1nuPTE1DowcErk cr4CnzMJHbIRZNoA4UpnOaF7sZQQT3PDafKohnx2v9xD2jcKJ2VTwe0daBj3KcsxUBrxEtRajrCxN gPUCkLZ+TUoPrKypqi7frsq+Saynn7QKXZcGWP/SdlieERfvSGk+i2b2r3XYRuECDMsb1AIer1HXJ zeJdC/7iMwOhlwFSPsyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p7Yz0-00CtWf-B7; Tue, 20 Dec 2022 09:32:23 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p7Ywf-00CsO2-4H for linux-arm-kernel@lists.infradead.org; Tue, 20 Dec 2022 09:30:00 +0000 Received: from dggpeml500002.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4NbrqL43BgzJqTP; Tue, 20 Dec 2022 17:28:46 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggpeml500002.china.huawei.com (7.185.36.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 20 Dec 2022 17:29:45 +0800 From: Junhao He To: , , , , CC: , , , , , , , , , , , Subject: [PATCH v15 2/2] Documentation: Add document for UltraSoc SMB driver Date: Tue, 20 Dec 2022 17:29:45 +0800 Message-ID: <20221220092945.30722-3-hejunhao3@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221220092945.30722-1-hejunhao3@huawei.com> References: <20221220092945.30722-1-hejunhao3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500002.china.huawei.com (7.185.36.158) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221220_012957_753238_0AFF276D X-CRM114-Status: GOOD ( 16.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Qi Liu Bring in documentation for UltraSoc SMB driver. It simply describes the device, sysfs interface and the firmware bindings. Signed-off-by: Qi Liu Signed-off-by: Junhao He Reviewed-by: Jonathan Cameron Reviewed-by: Bagas Sanjaya --- .../sysfs-bus-coresight-devices-ultra_smb | 31 +++++++ .../trace/coresight/ultrasoc-smb.rst | 83 +++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb new file mode 100644 index 000000000000..f6526882c627 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb @@ -0,0 +1,31 @@ +What: /sys/bus/coresight/devices/ultra_smb/enable_sink +Date: December 2022 +KernelVersion: 6.2 +Contact: Junhao He +Description: (RW) Add/remove a SMB device from a trace path. There can be + multiple sources for a single SMB device. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/buf_size +Date: December 2022 +KernelVersion: 6.2 +Contact: Junhao He +Description: (Read) Shows the buffer size of each UltraSoc SMB device. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/buf_status +Date: December 2022 +KernelVersion: 6.2 +Contact: Junhao He +Description: (Read) Shows the value held by UltraSoc SMB status register. + BIT(0) is zero means buffer is empty. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/read_pos +Date: December 2022 +KernelVersion: 6.2 +Contact: Junhao He +Description: (Read) Shows the value held by UltraSoc SMB Read Pointer register. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/write_pos +Date: December 2022 +KernelVersion: 6.2 +Contact: Junhao He +Description: (Read) Shows the value held by UltraSoc SMB Write Pointer register. diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst new file mode 100644 index 000000000000..056dd120e14c --- /dev/null +++ b/Documentation/trace/coresight/ultrasoc-smb.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +UltraSoc - HW Assisted Tracing on SoC +====================================== + :Author: Qi Liu + :Date: December 2022 + +Introduction +------------ + +UltraSoc SMB is a per SCCL (Super CPU Cluster) hardware. It provides a +way to buffer and store CPU trace messages in a region of shared system +memory. The device acts as a coresight sink device and the +corresponding trace generators (ETM) are attached as source devices. + +Sysfs files and directories +--------------------------- + +The SMB devices appear on the existing coresight bus alongside other +devices:: + + $# ls /sys/bus/coresight/devices/ + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 + +The ``ultra_smb`` names SMB device associated with SCCL.:: + + $# ls /sys/bus/coresight/devices/ultra_smb0 + enable_sink mgmt + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt + buf_size buf_status read_pos write_pos + +Key file items are: + + * ``read_pos``: Shows the value on the read pointer register. + * ``write_pos``: Shows the value on the write pointer register. + * ``buf_status``: Shows the value on the status register. + BIT(0) is zero value which means the buffer is empty. + * ``buf_size``: Shows the buffer size of each device. + +Firmware Bindings +----------------- + +The device is only supported with ACPI. Its binding describes device +identifier, resource information and graph structure. + +The device is identified as ACPI HID "HISI03A1". Device resources are allocated +using the _CRS method. Each device must present two base address; the first one +is the configuration base address of the device, the second one is the 32-bit +base address of shared system memory. + +Example:: + + Device(USMB) { \ + Name(_HID, "HISI03A1") \ + Name(_CRS, ResourceTemplate() { \ + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, NonCacheable, \ + ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \ + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, Cacheable, \ + ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \ + }) \ + Name(_DSD, Package() { \ + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \ + /* Use CoreSight Graph ACPI bindings to describe connections topology */ + Package() { \ + 0, \ + 1, \ + Package() { \ + 1, \ + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \ + 8, \ + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \ + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \ + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \ + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \ + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \ + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \ + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \ + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \ + } \ + } \ + }) \ + }