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Wed, 21 Dec 2022 13:07:05 -0800 (PST) Received: from localhost ([176.234.10.188]) by smtp.gmail.com with UTF8SMTPSA id x15-20020a1c7c0f000000b003c6bbe910fdsm4438944wmc.9.2022.12.21.13.07.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Dec 2022 13:07:05 -0800 (PST) From: Sasha Finkelstein To: u.kleine-koenig@pengutronix.de, thierry.reding@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sasha Finkelstein Subject: [PATCH v5 2/4] pwm: Add Apple PWM controller Date: Thu, 22 Dec 2022 00:06:46 +0300 Message-Id: <20221221210648.2735-3-fnkl.kernel@gmail.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20221221210648.2735-1-fnkl.kernel@gmail.com> References: <20221221210648.2735-1-fnkl.kernel@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221221_130710_549515_E888BB4D X-CRM114-Status: GOOD ( 27.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds the Apple PWM controller driver. Signed-off-by: Sasha Finkelstein Acked-by: Sven Peter --- drivers/pwm/Kconfig | 12 ++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-apple.c | 154 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 167 insertions(+) create mode 100644 drivers/pwm/pwm-apple.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..c3be11468414 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -51,6 +51,18 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_APPLE + tristate "Apple SoC PWM support" + depends on ARCH_APPLE || COMPILE_TEST + help + Generic PWM framework driver for PWM controller present on + Apple SoCs + + Say Y here if you have an ARM Apple laptop, otherwise say N + + To compile this driver as a module, choose M here: the module + will be called pwm-apple. + config PWM_ATMEL tristate "Atmel PWM support" depends on ARCH_AT91 || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..19899b912e00 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_APPLE) += pwm-apple.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c new file mode 100644 index 000000000000..09048b02b2f5 --- /dev/null +++ b/drivers/pwm/pwm-apple.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Driver for the Apple SoC PWM controller + * + * Copyright The Asahi Linux Contributors + * + * Limitations: + * - The writes to cycle registers are shadowed until a write to + * the control register. + * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output + * is a constant off signal. + */ + +#include +#include +#include +#include +#include +#include + +#define APPLE_PWM_CTRL 0x00 +#define APPLE_PWM_ON_CYCLES 0x1c +#define APPLE_PWM_OFF_CYCLES 0x18 + +#define APPLE_CTRL_ENABLE BIT(0) +#define APPLE_CTRL_MODE BIT(2) +#define APPLE_CTRL_UPDATE BIT(5) +#define APPLE_CTRL_TRIGGER BIT(9) +#define APPLE_CTRL_INVERT BIT(10) +#define APPLE_CTRL_OUTPUT_ENABLE BIT(14) + +struct apple_pwm { + struct pwm_chip chip; + void __iomem *base; + u64 clkrate; +}; + +static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct apple_pwm, chip); +} + +static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct apple_pwm *fpwm; + + if (state->polarity == PWM_POLARITY_INVERSED) + return -EINVAL; + + fpwm = to_apple_pwm(chip); + if (state->enabled) { + u64 on_cycles, off_cycles; + + on_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->duty_cycle, NSEC_PER_SEC); + if (on_cycles > 0xFFFFFFFF) + return -ERANGE; + + off_cycles = mul_u64_u64_div_u64(fpwm->clkrate, + state->period, NSEC_PER_SEC) - on_cycles; + if (off_cycles > 0xFFFFFFFF) + return -ERANGE; + + writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES); + writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES); + writel(APPLE_CTRL_ENABLE | APPLE_CTRL_OUTPUT_ENABLE | APPLE_CTRL_UPDATE, + fpwm->base + APPLE_PWM_CTRL); + } else { + writel(0, fpwm->base + APPLE_PWM_CTRL); + } + return 0; +} + +static void apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct apple_pwm *fpwm; + u32 on_cycles, off_cycles, ctrl; + + fpwm = to_apple_pwm(chip); + + ctrl = readl(fpwm->base + APPLE_PWM_CTRL); + on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES); + off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES); + + state->enabled = (ctrl & APPLE_CTRL_ENABLE) && (ctrl & APPLE_CTRL_OUTPUT_ENABLE); + state->polarity = PWM_POLARITY_NORMAL; + // on_cycles + off_cycles is 33 bits, NSEC_PER_SEC is 30, there is no overflow + state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate); + state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) * + NSEC_PER_SEC, fpwm->clkrate); +} + +static const struct pwm_ops apple_pwm_ops = { + .apply = apple_pwm_apply, + .get_state = apple_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int apple_pwm_probe(struct platform_device *pdev) +{ + struct apple_pwm *fpwm; + struct clk *clk; + int ret; + + fpwm = devm_kzalloc(&pdev->dev, sizeof(*fpwm), GFP_KERNEL); + if (!fpwm) + return -ENOMEM; + + fpwm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(fpwm->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(fpwm->base), "unable to map mmio"); + + clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock"); + + /* + * uses the 24MHz system clock on all existing devices, can only + * happen if the device tree is broken + */ + fpwm->clkrate = clk_get_rate(clk); + if (fpwm->clkrate > NSEC_PER_SEC) + return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range"); + + fpwm->chip.dev = &pdev->dev; + fpwm->chip.npwm = 1; + fpwm->chip.ops = &apple_pwm_ops; + + ret = devm_pwmchip_add(&pdev->dev, &fpwm->chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip"); + + return 0; +} + +static const struct of_device_id apple_pwm_of_match[] = { + { .compatible = "apple,s5l-fpwm" }, + {} +}; +MODULE_DEVICE_TABLE(of, apple_pwm_of_match); + +static struct platform_driver apple_pwm_driver = { + .probe = apple_pwm_probe, + .driver = { + .name = "apple-pwm", + .of_match_table = apple_pwm_of_match, + }, +}; +module_platform_driver(apple_pwm_driver); + +MODULE_DESCRIPTION("Apple SoC PWM driver"); +MODULE_LICENSE("Dual MIT/GPL");