| Message ID | 20221231220146.646-3-samuel@sholland.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | crypto: Allwinner D1 crypto support | expand |
Dne sobota, 31. december 2022 ob 23:01:44 CET je Samuel Holland napisal(a): > At least the D1 variant requires a separate clock for the TRNG. > Without this clock enabled, reading from /dev/hwrng reports: > > sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3 > > Experimentation shows that the necessary clock is the SoC's internal > RC oscillator. This makes sense, as noise from the oscillator can be > used as a source of entropy. > > Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
Le Sat, Dec 31, 2022 at 04:01:44PM -0600, Samuel Holland a écrit : > At least the D1 variant requires a separate clock for the TRNG. > Without this clock enabled, reading from /dev/hwrng reports: > > sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3 > > Experimentation shows that the necessary clock is the SoC's internal > RC oscillator. This makes sense, as noise from the oscillator can be > used as a source of entropy. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > Acked-by: Corentin Labbe <clabbe.montjoie@gmail.com> Thanks
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c index 9f6594699835..a6865ff4d400 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c @@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_variant = { { "bus", 0, 200000000 }, { "mod", 300000000, 0 }, { "ram", 0, 400000000 }, + { "trng", 0, 0 }, }, .esr = ESR_D1, .prng = CE_ALG_PRNG, diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h index 8177aaba4434..27029fb77e29 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h @@ -105,7 +105,7 @@ #define MAX_SG 8 -#define CE_MAX_CLOCKS 3 +#define CE_MAX_CLOCKS 4 #define MAXFLOW 4
At least the D1 variant requires a separate clock for the TRNG. Without this clock enabled, reading from /dev/hwrng reports: sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3 Experimentation shows that the necessary clock is the SoC's internal RC oscillator. This makes sense, as noise from the oscillator can be used as a source of entropy. Signed-off-by: Samuel Holland <samuel@sholland.org> --- Changes in v2: - New patch for v2 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 + drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)