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[7/9] arm64: dts: mediatek: mt8186: Add DPI node

Message ID 20230111123711.32020-8-allen-kh.cheng@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add and update some driver nodes for MT8186 SoC | expand

Commit Message

Allen-KH Cheng Jan. 11, 2023, 12:37 p.m. UTC 
Add DPI node for MT8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

Chen-Yu Tsai Jan. 12, 2023, 11:48 a.m. UTC | #1 
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<allen-kh.cheng@mediatek.com> wrote:
>
> Add DPI node for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index c52f9be1e750..eab30ab01572 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1230,6 +1230,23 @@
>                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
>                 };
>
> +               dpi0: dpi@1400a000 {

You could drop the trailing 0 in the label, since there is only one
instance.

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

> +                       compatible = "mediatek,mt8186-dpi";
> +                       reg = <0 0x1400a000 0 0x1000>;
> +                       clocks = <&topckgen CLK_TOP_DPI>,
> +                                <&mmsys CLK_MM_DISP_DPI>,
> +                                <&apmixedsys CLK_APMIXED_TVDPLL>;
> +                       clock-names = "pixel", "engine", "pll";
> +                       assigned-clocks = <&topckgen CLK_TOP_DPI>;
> +                       assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
> +                       interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
> +                       status = "disabled";
> +
> +                       port {
> +                               dpi_out: endpoint { };
> +                       };
> +               };
> +
>                 dsi0: dsi@14013000 {
>                         compatible = "mediatek,mt8186-dsi";
>                         reg = <0 0x14013000 0 0x1000>;
> --
> 2.18.0
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c52f9be1e750..eab30ab01572 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1230,6 +1230,23 @@ 
 			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
 		};
 
+		dpi0: dpi@1400a000 {
+			compatible = "mediatek,mt8186-dpi";
+			reg = <0 0x1400a000 0 0x1000>;
+			clocks = <&topckgen CLK_TOP_DPI>,
+				 <&mmsys CLK_MM_DISP_DPI>,
+				 <&apmixedsys CLK_APMIXED_TVDPLL>;
+			clock-names = "pixel", "engine", "pll";
+			assigned-clocks = <&topckgen CLK_TOP_DPI>;
+			assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
+			status = "disabled";
+
+			port {
+				dpi_out: endpoint { };
+			};
+		};
+
 		dsi0: dsi@14013000 {
 			compatible = "mediatek,mt8186-dsi";
 			reg = <0 0x14013000 0 0x1000>;