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Fri, 13 Jan 2023 14:37:57 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 13 Jan 2023 06:37:49 -0800 From: devi priya To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 6/6] clk: qcom: Fix APSS PLL and RCG Configuration Date: Fri, 13 Jan 2023 20:06:47 +0530 Message-ID: <20230113143647.14961-7-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230113143647.14961-1-quic_devipriy@quicinc.com> References: <20230113143647.14961-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dfOSr7wANXk6JETj8MnbsuzSbz2-IxvR X-Proofpoint-ORIG-GUID: dfOSr7wANXk6JETj8MnbsuzSbz2-IxvR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-13_06,2023-01-13_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxlogscore=922 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301130096 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230113_063809_029040_3C390431 X-CRM114-Status: GOOD ( 17.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Included CLK_IS_CRITICAL flag which helps to properly enable the APSS PLL during bootup. clk_rcg2_ops should be used for APSS clock RCG, as other ops will not configure the RCG register Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: devi priya --- drivers/clk/qcom/apss-ipq-pll.c | 1 + drivers/clk/qcom/apss-ipq6018.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index dd0c01bf5a98..75486a124fcd 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -33,6 +33,7 @@ static struct clk_alpha_pll ipq_pll = { }, .num_parents = 1, .ops = &clk_alpha_pll_huayra_ops, + .flags = CLK_IS_CRITICAL, }, }, }; diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c index f2f502e2d5a4..0d0e7196a4dc 100644 --- a/drivers/clk/qcom/apss-ipq6018.c +++ b/drivers/clk/qcom/apss-ipq6018.c @@ -33,15 +33,21 @@ static const struct parent_map parents_apcs_alias0_clk_src_map[] = { { P_APSS_PLL_EARLY, 5 }, }; +static const struct freq_tbl ftbl_apcs_alias0_clk_src[] = { + { .src = P_APSS_PLL_EARLY, .pre_div = 1 }, + { } +}; + static struct clk_rcg2 apcs_alias0_clk_src = { .cmd_rcgr = 0x0050, + .freq_tbl = ftbl_apcs_alias0_clk_src, .hid_width = 5, .parent_map = parents_apcs_alias0_clk_src_map, .clkr.hw.init = &(struct clk_init_data){ .name = "apcs_alias0_clk_src", .parent_data = parents_apcs_alias0_clk_src, .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), - .ops = &clk_rcg2_mux_closest_ops, + .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, }, };