Message ID | 20230125104520.89684-4-quic_kathirav@quicinc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add minimal boot support for IPQ5332 | expand |
Quoting Kathiravan Thirumoorthy (2023-01-25 02:45:13) > From: Kathiravan T <quic_kathirav@quicinc.com> > > Add the support for stromer plus pll, which is found on the IPQ5332 > SoCs. Programming sequence is same as the stromer pll, so we can re-use > the same. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org> I'm amazed that we need so many different register layouts for PLLs. Was it really never standardized? So sad.
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index d841ec414072..cd23a85e27c4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -216,6 +216,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x34, [PLL_OFF_STATUS] = 0x28, }, + [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_USER_CTL] = 0x08, + [PLL_OFF_USER_CTL_U] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_TEST_CTL] = 0x14, + [PLL_OFF_TEST_CTL_U] = 0x18, + [PLL_OFF_STATUS] = 0x1c, + [PLL_OFF_ALPHA_VAL] = 0x24, + [PLL_OFF_ALPHA_VAL_U] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 33b8badb9fb0..64c492fc2288 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -27,6 +27,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, + CLK_ALPHA_PLL_TYPE_STROMER_PLUS, CLK_ALPHA_PLL_TYPE_MAX, };