@@ -346,7 +346,7 @@
* bits in PAR are res0.
*/
#define PAR_TO_HPFAR(par) \
- (((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
+ (((par) & GENMASK_ULL(MAX_PHYS_MASK_SHIFT - 1, 12)) >> 8)
#define ECN(x) { ESR_ELx_EC_##x, #x }
@@ -178,8 +178,8 @@
/*
* Highest possible physical address supported.
*/
-#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
-#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
+#define MAX_PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
+#define MAX_PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
#define TTBR_CNP_BIT (UL(1) << 0)
@@ -35,6 +35,11 @@
#include <linux/sched.h>
#include <linux/page_table_check.h>
+extern unsigned int phys_mask_shift;
+
+#define PHYS_MASK_SHIFT (phys_mask_shift)
+#define PHYS_MASK ((1UL << PHYS_MASK_SHIFT) - 1)
+
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
@@ -321,7 +321,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
#error "Mismatch between VA_BITS and page size/number of translation levels"
#endif
#else
-#define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT)
+#define IDMAP_PGD_ORDER (MAX_PHYS_MASK_SHIFT - PGDIR_SHIFT)
#define EXTRA_SHIFT
/*
* If VA_BITS == 48, we don't have to configure an additional
@@ -12,6 +12,8 @@ struct realm_config __attribute((aligned(PAGE_SIZE))) config;
unsigned long prot_ns_shared;
EXPORT_SYMBOL(prot_ns_shared);
+unsigned int phys_mask_shift = CONFIG_ARM64_PA_BITS;
+
DEFINE_STATIC_KEY_FALSE_RO(rsi_present);
static bool rsi_version_matches(void)
@@ -54,5 +56,8 @@ void __init arm64_rsi_init(void)
return;
prot_ns_shared = BIT(config.ipa_bits - 1);
+ if (config.ipa_bits - 1 < phys_mask_shift)
+ phys_mask_shift = config.ipa_bits - 1;
+
static_branch_enable(&rsi_present);
}