diff mbox series

[3/3] dt-bindings: iommu: memory: Use unmanaged iommu domain for the APU

Message ID 20230130102722.133271-4-abailon@baylibre.com (mailing list archive)
State New, archived
Headers show
Series Add support of unmanaged domain to mediatek IOMMU | expand

Commit Message

Alexandre Bailon Jan. 30, 2023, 10:27 a.m. UTC
This updates the iommu id to use unmanaged iommu domain for the APU.
This is required by remoteproc to use the iommu.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
---
 include/dt-bindings/memory/mediatek,mt8365-larb-port.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Alexandre Mergnat Jan. 30, 2023, 12:04 p.m. UTC | #1
On 30/01/2023 11:27, Alexandre Bailon wrote:
> This updates the iommu id to use unmanaged iommu domain for the APU.
> This is required by remoteproc to use the iommu.
> 
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>

Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Rob Herring Jan. 30, 2023, 10:50 p.m. UTC | #2
On Mon, Jan 30, 2023 at 11:27:22AM +0100, Alexandre Bailon wrote:
> This updates the iommu id to use unmanaged iommu domain for the APU.
> This is required by remoteproc to use the iommu.

Explain how a mixture of DTs with or without this value changed would 
work with kernels with or without support for unmanaged domains? Looks 
like a compatibility problem to me.

> 
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> ---
>  include/dt-bindings/memory/mediatek,mt8365-larb-port.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
> index 56d5a5dd519e7..86d82a8f6017d 100644
> --- a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
> +++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
> @@ -24,8 +24,8 @@
>  #define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
>  #define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB0_ID, 8)
>  #define M4U_PORT_DISP_FAKE0		MTK_M4U_ID(M4U_LARB0_ID, 9)
> -#define M4U_PORT_APU_READ		MTK_M4U_ID(M4U_LARB0_ID, 10)
> -#define M4U_PORT_APU_WRITE		MTK_M4U_ID(M4U_LARB0_ID, 11)
> +#define M4U_PORT_APU_READ		MTK_M4U_UNMANAGED_ID(M4U_LARB0_ID, 10)
> +#define M4U_PORT_APU_WRITE		MTK_M4U_UNMANAGED_ID(M4U_LARB0_ID, 11)
>  
>  /* larb1 */
>  #define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB1_ID, 0)
> -- 
> 2.38.2
>
diff mbox series

Patch

diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
index 56d5a5dd519e7..86d82a8f6017d 100644
--- a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
+++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
@@ -24,8 +24,8 @@ 
 #define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
 #define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB0_ID, 8)
 #define M4U_PORT_DISP_FAKE0		MTK_M4U_ID(M4U_LARB0_ID, 9)
-#define M4U_PORT_APU_READ		MTK_M4U_ID(M4U_LARB0_ID, 10)
-#define M4U_PORT_APU_WRITE		MTK_M4U_ID(M4U_LARB0_ID, 11)
+#define M4U_PORT_APU_READ		MTK_M4U_UNMANAGED_ID(M4U_LARB0_ID, 10)
+#define M4U_PORT_APU_WRITE		MTK_M4U_UNMANAGED_ID(M4U_LARB0_ID, 11)
 
 /* larb1 */
 #define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB1_ID, 0)