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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id s5-20020a5d5105000000b002bdfcd8c77csm11426785wrt.101.2023.01.30.02.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 02:26:39 -0800 (PST) From: Alexandre Bailon To: yong.wu@mediatek.com, joro@8bytes.org, will@kernel.org Cc: robin.murphy@arm.com, matthias.bgg@gmail.com, krzysztof.kozlowski@linaro.org, robh+dt@kernel.org, iommu@lists.linux.dev, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexandre Bailon Subject: [PATCH 3/3] dt-bindings: iommu: memory: Use unmanaged iommu domain for the APU Date: Mon, 30 Jan 2023 11:27:22 +0100 Message-Id: <20230130102722.133271-4-abailon@baylibre.com> X-Mailer: git-send-email 2.38.2 In-Reply-To: <20230130102722.133271-1-abailon@baylibre.com> References: <20230130102722.133271-1-abailon@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230130_022641_176575_2AC39036 X-CRM114-Status: GOOD ( 11.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This updates the iommu id to use unmanaged iommu domain for the APU. This is required by remoteproc to use the iommu. Signed-off-by: Alexandre Bailon Reviewed-by: Alexandre Mergnat --- include/dt-bindings/memory/mediatek,mt8365-larb-port.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h index 56d5a5dd519e7..86d82a8f6017d 100644 --- a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h +++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h @@ -24,8 +24,8 @@ #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8) #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) -#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10) -#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11) +#define M4U_PORT_APU_READ MTK_M4U_UNMANAGED_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_APU_WRITE MTK_M4U_UNMANAGED_ID(M4U_LARB0_ID, 11) /* larb1 */ #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0)