From patchwork Wed Feb 1 12:53:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 13124405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6F9DC05027 for ; Wed, 1 Feb 2023 14:24:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=c8haw7y5v8YtfJfTn4esebNt1lWAoUdq1BloZ8L3VO8=; b=Zq3LpLkJHY0Y+w Wbu2Lvoyj4+Rh7kleOUBgyiNvOq1e0Q43g6BleCmEUwMjRT52+Qu8K3bNCBCJ1olV87N4dibPo+dN i4BafKRvNbKrrk7VbCPL31E+d9DRN4LIHm7FSTBldIKHzVWz8NpTyRzHEXMpncnexG6e8X0FZBEgk bSANIY7ULl82jYH/TLzAdDx2s1kxFx6ZHKPVNlxzI7Zp8xW2HutrHDhjV/kf3lCnjkrJJdPhXuLyv pNE0/BRrM8ZiUrLSz741lbq3nXgH2oNT1hZHh3FfGHXJZzH4YeOJYdby2sq7kEYdh7G5LDlo4QM7o Lfi3aUflTPfbfIP7yn9g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNE17-00CJnr-26; Wed, 01 Feb 2023 14:23:17 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNDhS-00CBgK-D1 for linux-arm-kernel@bombadil.infradead.org; Wed, 01 Feb 2023 14:02:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=U/1E+V5Gw5Rx46TOmlvRjgOfJHiZaXebZrwYicZFtkM=; b=M4dpgRPiS74nDY5W6VD1rHSGcW td6oBqT3mcXrFSv3KlLKRyZvRL1yDSUdcXCxWRrkoDw5E5riM+tsmJJICRR5QFHz5dc2IyigKsF0r y1KFL4TAhwbkA7nvJfYM8jzixBIh2LO2//jHNWNDXtN3Vcr2TfqkFyAfXn5uw6cym5EmQ2jE3BlY/ wuzJn9PrGZvmaSC0VCkZBIKFlRJgBHSreQqqcysfvdzCV0JaQClJBGJ/3TgkkMfpG0+p0YdTHYdVb pUGrR89TqV1NgXGlFdqkNA4mL5mgsa9TjcqydTh2rQW8e3jPLXv1TYApYhZn+eTTy4CgEXMZxSuz0 2LcjjZUA==; Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by desiato.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pNChb-004m1w-0R for linux-arm-kernel@lists.infradead.org; Wed, 01 Feb 2023 12:59:22 +0000 Received: by mail-wr1-x434.google.com with SMTP id h16so17197003wrz.12 for ; Wed, 01 Feb 2023 04:59:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U/1E+V5Gw5Rx46TOmlvRjgOfJHiZaXebZrwYicZFtkM=; b=rbZDUky7hyOUseO47rt8pNa6lE8iRS4ovMkNWarTthOMVpGeSQTtP9qSj/majBB5iD vOznM2LLhpX3MQkqjmXs3AYAF8ghw1OTIEDc76WKJQrvnjh8u0YE9fDgf1Z3b3FrEGW7 pLkItik7KqD7NZnCEul3NZTQpobfUf3cdZGPN9vwUxyAxwJp8RWyqiEdT1difM66qKSX 4xlI7H73dui8mKy5RjxRRlqu1QvGnVfkF8xvsTjM0yHEq/DN+YRnjVrw9cf8hIVX6PL8 XZMuV64GrB2ooxI9UVxJZ0/Ua+0tPoE/N76WNmcnBctnBf8INDZ2DepTqt98rmNCRuus Lh+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U/1E+V5Gw5Rx46TOmlvRjgOfJHiZaXebZrwYicZFtkM=; b=1bkh4OmRk9TVQsH6gIcXIrk/fF9dpU1R4JB1Nv8n9c+2GmQ062b2UohjiFgYPR0Xzo Ja9TofexbjrjIJ9bm0v83ER4qsOFLsXVn1TXxWiwA7O0lycNL7eO8VI3ZT2lI+Wr/6EI VDA+ElJb8Wp4nAvjQopX7mWOON58jbwtXO+69OsCe4ELiapReldAersfRUWQfDHeUcif MhWKCpL2Fw3/BmyHio2ZVBNX7FJ3A7Pb6fbDROUvd9crYG+mAfYuVvnqXOSBRGg9DCbo cBZHqUyjXds1xL5UADY7v181G7HsFAtK0qZ97PyiJAQKKYilTK5LV9kWEANexINfxIBc lQbQ== X-Gm-Message-State: AO0yUKW7xMqZs/Rg30lwcdcNOpZpb5yXwapvU5BP5crhjzzL8tmR6wrg exJER/clWTKudYNXjrWAex110A== X-Google-Smtp-Source: AK7set9e0pBWb6kGtQQaKRSuYaYQ3aayGueAvARL6oWlBrFe/ohTg7/zUWlhu/MDSt+NySkK0eZRyA== X-Received: by 2002:adf:ef05:0:b0:2bf:d72b:d039 with SMTP id e5-20020adfef05000000b002bfd72bd039mr2394106wro.10.1675256376784; Wed, 01 Feb 2023 04:59:36 -0800 (PST) Received: from localhost.localdomain (054592b0.skybroadband.com. [5.69.146.176]) by smtp.gmail.com with ESMTPSA id m15-20020a056000024f00b002bfae16ee2fsm17972811wrz.111.2023.02.01.04.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 04:59:36 -0800 (PST) From: Jean-Philippe Brucker To: maz@kernel.org, catalin.marinas@arm.com, will@kernel.org, joro@8bytes.org Cc: robin.murphy@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, smostafa@google.com, dbrazdil@google.com, ryan.roberts@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, Jean-Philippe Brucker Subject: [RFC PATCH 22/45] KVM: arm64: smmu-v3: Initialize registers Date: Wed, 1 Feb 2023 12:53:06 +0000 Message-Id: <20230201125328.2186498-23-jean-philippe@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230201125328.2186498-1-jean-philippe@linaro.org> References: <20230201125328.2186498-1-jean-philippe@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230201_125903_502900_2B5A5219 X-CRM114-Status: GOOD ( 18.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Ensure all writable registers are properly initialized. We do not touch registers that will not be read by the SMMU due to disabled features, such as event queue registers. Signed-off-by: Jean-Philippe Brucker --- include/kvm/arm_smmu_v3.h | 11 +++ arch/arm64/kvm/hyp/nvhe/iommu/arm-smmu-v3.c | 103 +++++++++++++++++++- 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/include/kvm/arm_smmu_v3.h b/include/kvm/arm_smmu_v3.h index ebe488b2f93c..d4b1e487b7d7 100644 --- a/include/kvm/arm_smmu_v3.h +++ b/include/kvm/arm_smmu_v3.h @@ -7,8 +7,19 @@ #if IS_ENABLED(CONFIG_ARM_SMMU_V3_PKVM) +/* + * Parameters from the trusted host: + * @mmio_addr base address of the SMMU registers + * @mmio_size size of the registers resource + * + * Other members are filled and used at runtime by the SMMU driver. + */ struct hyp_arm_smmu_v3_device { struct kvm_hyp_iommu iommu; + phys_addr_t mmio_addr; + size_t mmio_size; + + void __iomem *base; }; extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); diff --git a/arch/arm64/kvm/hyp/nvhe/iommu/arm-smmu-v3.c b/arch/arm64/kvm/hyp/nvhe/iommu/arm-smmu-v3.c index c167e4dbd28d..75a6aa01b057 100644 --- a/arch/arm64/kvm/hyp/nvhe/iommu/arm-smmu-v3.c +++ b/arch/arm64/kvm/hyp/nvhe/iommu/arm-smmu-v3.c @@ -4,16 +4,117 @@ * * Copyright (C) 2022 Linaro Ltd. */ +#include #include #include #include +#include +#include + +#define ARM_SMMU_POLL_TIMEOUT_US 1000000 /* 1s! */ size_t __ro_after_init kvm_hyp_arm_smmu_v3_count; struct hyp_arm_smmu_v3_device __ro_after_init *kvm_hyp_arm_smmu_v3_smmus; +#define for_each_smmu(smmu) \ + for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \ + (smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \ + (smmu)++) + +/* + * Wait until @cond is true. + * Return 0 on success, or -ETIMEDOUT + */ +#define smmu_wait(_cond) \ +({ \ + int __i = 0; \ + int __ret = 0; \ + \ + while (!(_cond)) { \ + if (++__i > ARM_SMMU_POLL_TIMEOUT_US) { \ + __ret = -ETIMEDOUT; \ + break; \ + } \ + pkvm_udelay(1); \ + } \ + __ret; \ +}) + +static int smmu_write_cr0(struct hyp_arm_smmu_v3_device *smmu, u32 val) +{ + writel_relaxed(val, smmu->base + ARM_SMMU_CR0); + return smmu_wait(readl_relaxed(smmu->base + ARM_SMMU_CR0ACK) == val); +} + +static int smmu_init_registers(struct hyp_arm_smmu_v3_device *smmu) +{ + u64 val, old; + + if (!(readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_ABORT)) + return -EINVAL; + + /* Initialize all RW registers that will be read by the SMMU */ + smmu_write_cr0(smmu, 0); + + val = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) | + FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB); + writel_relaxed(val, smmu->base + ARM_SMMU_CR1); + writel_relaxed(CR2_PTM, smmu->base + ARM_SMMU_CR2); + writel_relaxed(0, smmu->base + ARM_SMMU_IRQ_CTRL); + + val = readl_relaxed(smmu->base + ARM_SMMU_GERROR); + old = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + /* Service Failure Mode is fatal */ + if ((val ^ old) & GERROR_SFM_ERR) + return -EIO; + /* Clear pending errors */ + writel_relaxed(val, smmu->base + ARM_SMMU_GERRORN); + + return 0; +} + +static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu) +{ + int ret; + + if (!PAGE_ALIGNED(smmu->mmio_addr | smmu->mmio_size)) + return -EINVAL; + + ret = pkvm_create_hyp_device_mapping(smmu->mmio_addr, smmu->mmio_size, + &smmu->base); + if (IS_ERR(smmu->base)) + return PTR_ERR(smmu->base); + + ret = smmu_init_registers(smmu); + if (ret) + return ret; + + return 0; +} + static int smmu_init(void) { - return -ENOSYS; + int ret; + struct hyp_arm_smmu_v3_device *smmu; + + ret = pkvm_create_mappings(kvm_hyp_arm_smmu_v3_smmus, + kvm_hyp_arm_smmu_v3_smmus + + kvm_hyp_arm_smmu_v3_count, + PAGE_HYP); + if (ret) + return ret; + + for_each_smmu(smmu) { + ret = smmu_init_device(smmu); + if (ret) + return ret; + } + + return 0; } static struct kvm_iommu_ops smmu_ops = {