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[5.69.146.176]) by smtp.gmail.com with ESMTPSA id m15-20020a056000024f00b002bfae16ee2fsm17972811wrz.111.2023.02.01.04.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 04:59:49 -0800 (PST) From: Jean-Philippe Brucker To: maz@kernel.org, catalin.marinas@arm.com, will@kernel.org, joro@8bytes.org Cc: robin.murphy@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, smostafa@google.com, dbrazdil@google.com, ryan.roberts@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, Jean-Philippe Brucker Subject: [RFC PATCH 39/45] iommu/arm-smmu-v3-kvm: Initialize page table configuration Date: Wed, 1 Feb 2023 12:53:23 +0000 Message-Id: <20230201125328.2186498-40-jean-philippe@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230201125328.2186498-1-jean-philippe@linaro.org> References: <20230201125328.2186498-1-jean-philippe@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230201_045950_897024_7AD8DFC2 X-CRM114-Status: GOOD ( 16.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Prepare the stage-2 I/O page table configuration that will be used by the hypervisor driver. Signed-off-by: Jean-Philippe Brucker --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c index 755c77bc0417..55489d56fb5b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kvm.c @@ -16,6 +16,7 @@ struct host_arm_smmu_device { struct arm_smmu_device smmu; pkvm_handle_t id; u32 boot_gbpa; + unsigned int pgd_order; }; #define smmu_to_host(_smmu) \ @@ -192,6 +193,7 @@ static int kvm_arm_smmu_probe(struct platform_device *pdev) size_t size; phys_addr_t ioaddr; struct resource *res; + struct io_pgtable_cfg cfg; struct arm_smmu_device *smmu; struct device *dev = &pdev->dev; struct host_arm_smmu_device *host_smmu; @@ -233,6 +235,31 @@ static int kvm_arm_smmu_probe(struct platform_device *pdev) if (!kvm_arm_smmu_validate_features(smmu)) return -ENODEV; + /* + * Stage-1 should be easy to support, though we do need to allocate a + * context descriptor table. + */ + cfg = (struct io_pgtable_cfg) { + .fmt = ARM_64_LPAE_S2, + .pgsize_bitmap = smmu->pgsize_bitmap, + .ias = smmu->ias, + .oas = smmu->oas, + .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, + }; + + /* + * Choose the page and address size. Compute the PGD size and number of + * levels as well, so we know how much memory to pre-allocate. + */ + ret = io_pgtable_configure(&cfg, &size); + if (ret) + return ret; + + host_smmu->pgd_order = get_order(size); + smmu->pgsize_bitmap = cfg.pgsize_bitmap; + smmu->ias = cfg.ias; + smmu->oas = cfg.oas; + ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, ARM_SMMU_CMDQ_PROD, ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS, "cmdq"); @@ -253,6 +280,8 @@ static int kvm_arm_smmu_probe(struct platform_device *pdev) hyp_smmu->mmio_addr = ioaddr; hyp_smmu->mmio_size = size; hyp_smmu->features = smmu->features; + hyp_smmu->iommu.pgtable_cfg = cfg; + kvm_arm_smmu_cur++; return 0;