| Message ID | 20230202150619.22425-7-quic_devipriy@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add minimal boot support for IPQ9574 | expand |
On 2/2/2023 8:36 PM, Devi Priya wrote: > Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board > > Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> > Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> > Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com> > Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com> > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 84 ++++++ > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 278 +++++++++++++++++++ > 3 files changed, 363 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts > create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 557d77d48dc8..562952c76f7a 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb > dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb > dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb > dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb > +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb Please use tab. > dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb > dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb > dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts > new file mode 100644 > index 000000000000..2c8430197ec0 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts > @@ -0,0 +1,84 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * IPQ9574 AL02-C7 board device tree source > + * > + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. > + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include "ipq9574.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; > + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; > + > + aliases { > + serial0 = &blsp1_uart2; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&blsp1_uart2 { > + pinctrl-0 = <&uart2_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&sdhc_1 { > + pinctrl-0 = <&sdc_default_state>; > + pinctrl-names = "default"; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + mmc-hs400-enhanced-strobe; > + max-frequency = <384000000>; > + bus-width = <8>; > + status = "okay"; > +}; > + > +&sleep_clk { > + clock-frequency = <32000>; > +}; > + > +&tlmm { > + sdc_default_state: sdc-default-state { > + clk-pins { > + pins = "gpio5"; > + function = "sdc_clk"; > + drive-strength = <8>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "gpio4"; > + function = "sdc_cmd"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "gpio0", "gpio1", "gpio2", > + "gpio3", "gpio6", "gpio7", > + "gpio8", "gpio9"; > + function = "sdc_data"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + > + rclk-pins { > + pins = "gpio10"; > + function = "sdc_rclk"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + }; > +}; > + > +&xo_board_clk { > + clock-frequency = <24000000>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > new file mode 100644 > index 000000000000..2b86ba17bb32 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -0,0 +1,278 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * IPQ9574 SoC device tree source > + * > + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,ipq9574-gcc.h> > +#include <dt-bindings/reset/qcom,ipq9574-gcc.h> > + > +/ { > + interrupt-parent = <&intc>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + clocks { > + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { > + compatible = "fixed-clock"; > + clock-frequency = <353000000>; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + xo_board_clk: xo-board-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x0>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x1>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x2>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + CPU3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x3>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + }; > + > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0x0 0x40000000 0x0 0x0>; > + }; > + > + pmu { > + compatible = "arm,cortex-a73-pmu"; > + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + tz_region: tz@4a600000 { > + reg = <0x0 0x4a600000 0x0 0x400000>; > + no-map; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0 0xffffffff>; > + > + tlmm: pinctrl@1000000 { > + compatible = "qcom,ipq9574-tlmm"; > + reg = <0x01000000 0x300000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&tlmm 0 0 65>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + uart2_pins: uart2-state { > + pins = "gpio34", "gpio35"; > + function = "blsp2_uart"; > + drive-strength = <8>; > + bias-disable; > + }; > + }; > + > + gcc: clock-controller@1800000 { > + compatible = "qcom,ipq9574-gcc"; > + reg = <0x01800000 0x80000>; > + clocks = <&xo_board_clk>, > + <&sleep_clk>, > + <&bias_pll_ubi_nc_clk>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + clock-names = "xo", > + "sleep_clk", > + "bias_pll_ubi_nc_clk", > + "pcie30_phy0_pipe_clk", > + "pcie30_phy1_pipe_clk", > + "pcie30_phy2_pipe_clk", > + "pcie30_phy3_pipe_clk", > + "usb3phy_0_cc_pipe_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + sdhc_1: mmc@7804000 { > + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; > + reg-names = "hc", "cqhci"; > + > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&xo_board_clk>; > + clock-names = "iface", "core", "xo"; > + non-removable; > + status = "disabled"; > + }; > + > + blsp1_uart2: serial@78b1000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0x078b1000 0x200>; > + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, > + <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > + intc: interrupt-controller@b000000 { > + compatible = "qcom,msm-qgic2"; > + reg = <0x0b000000 0x1000>, /* GICD */ > + <0x0b002000 0x1000>, /* GICC */ > + <0x0b001000 0x1000>, /* GICH */ > + <0x0b004000 0x1000>; /* GICV */ > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + ranges = <0 0x0b00c000 0x3000>; > + > + v2m0: v2m@0 { > + compatible = "arm,gic-v2m-frame"; > + reg = <0x00000000 0xffd>; > + msi-controller; > + }; > + > + v2m1: v2m@1000 { > + compatible = "arm,gic-v2m-frame"; > + reg = <0x00001000 0xffd>; > + msi-controller; > + }; > + > + v2m2: v2m@2000 { > + compatible = "arm,gic-v2m-frame"; > + reg = <0x00002000 0xffd>; > + msi-controller; > + }; > + }; > + > + timer@b120000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0b120000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + frame@b120000 { > + reg = <0x0b121000 0x1000>, > + <0x0b122000 0x1000>; > + frame-number = <0>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + frame@b123000 { > + reg = <0x0b123000 0x1000>; > + frame-number = <1>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@b124000 { > + reg = <0x0b124000 0x1000>; > + frame-number = <2>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@b125000 { > + reg = <0x0b125000 0x1000>; > + frame-number = <3>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@b126000 { > + reg = <0x0b126000 0x1000>; > + frame-number = <4>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@b127000 { > + reg = <0x0b127000 0x1000>; > + frame-number = <5>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + frame@b128000 { > + reg = <0x0b128000 0x1000>; > + frame-number = <6>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > +};
On 2/3/2023 11:23 AM, Kathiravan T wrote: > > On 2/2/2023 8:36 PM, Devi Priya wrote: >> Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board >> >> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> >> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> >> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com> >> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 84 ++++++ >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 278 +++++++++++++++++++ >> 3 files changed, 363 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts >> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile >> b/arch/arm64/boot/dts/qcom/Makefile >> index 557d77d48dc8..562952c76f7a 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb > > > Please use tab. > Sure, okay > >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts >> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts >> new file mode 100644 >> index 000000000000..2c8430197ec0 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts >> @@ -0,0 +1,84 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) >> +/* >> + * IPQ9574 AL02-C7 board device tree source >> + * >> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. >> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights >> reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include "ipq9574.dtsi" >> + >> +/ { >> + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; >> + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; >> + >> + aliases { >> + serial0 = &blsp1_uart2; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> +}; >> + >> +&blsp1_uart2 { >> + pinctrl-0 = <&uart2_pins>; >> + pinctrl-names = "default"; >> + status = "okay"; >> +}; >> + >> +&sdhc_1 { >> + pinctrl-0 = <&sdc_default_state>; >> + pinctrl-names = "default"; >> + mmc-ddr-1_8v; >> + mmc-hs200-1_8v; >> + mmc-hs400-1_8v; >> + mmc-hs400-enhanced-strobe; >> + max-frequency = <384000000>; >> + bus-width = <8>; >> + status = "okay"; >> +}; >> + >> +&sleep_clk { >> + clock-frequency = <32000>; >> +}; >> + >> +&tlmm { >> + sdc_default_state: sdc-default-state { >> + clk-pins { >> + pins = "gpio5"; >> + function = "sdc_clk"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "gpio4"; >> + function = "sdc_cmd"; >> + drive-strength = <8>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "gpio0", "gpio1", "gpio2", >> + "gpio3", "gpio6", "gpio7", >> + "gpio8", "gpio9"; >> + function = "sdc_data"; >> + drive-strength = <8>; >> + bias-pull-up; >> + }; >> + >> + rclk-pins { >> + pins = "gpio10"; >> + function = "sdc_rclk"; >> + drive-strength = <8>; >> + bias-pull-down; >> + }; >> + }; >> +}; >> + >> +&xo_board_clk { >> + clock-frequency = <24000000>; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> new file mode 100644 >> index 000000000000..2b86ba17bb32 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -0,0 +1,278 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) >> +/* >> + * IPQ9574 SoC device tree source >> + * >> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. >> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights >> reserved. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h> >> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h> >> + >> +/ { >> + interrupt-parent = <&intc>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clocks { >> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <353000000>; >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; >> + >> + xo_board_clk: xo-board-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + CPU0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a73"; >> + reg = <0x0>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + CPU1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a73"; >> + reg = <0x1>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + CPU2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a73"; >> + reg = <0x2>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + CPU3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a73"; >> + reg = <0x3>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + L2_0: l2-cache { >> + compatible = "cache"; >> + cache-level = <2>; >> + }; >> + }; >> + >> + memory@40000000 { >> + device_type = "memory"; >> + /* We expect the bootloader to fill in the size */ >> + reg = <0x0 0x40000000 0x0 0x0>; >> + }; >> + >> + pmu { >> + compatible = "arm,cortex-a73-pmu"; >> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | >> IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + }; >> + >> + reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + tz_region: tz@4a600000 { >> + reg = <0x0 0x4a600000 0x0 0x400000>; >> + no-map; >> + }; >> + }; >> + >> + soc: soc@0 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0 0 0xffffffff>; >> + >> + tlmm: pinctrl@1000000 { >> + compatible = "qcom,ipq9574-tlmm"; >> + reg = <0x01000000 0x300000>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + gpio-ranges = <&tlmm 0 0 65>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + >> + uart2_pins: uart2-state { >> + pins = "gpio34", "gpio35"; >> + function = "blsp2_uart"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> + >> + gcc: clock-controller@1800000 { >> + compatible = "qcom,ipq9574-gcc"; >> + reg = <0x01800000 0x80000>; >> + clocks = <&xo_board_clk>, >> + <&sleep_clk>, >> + <&bias_pll_ubi_nc_clk>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>; >> + clock-names = "xo", >> + "sleep_clk", >> + "bias_pll_ubi_nc_clk", >> + "pcie30_phy0_pipe_clk", >> + "pcie30_phy1_pipe_clk", >> + "pcie30_phy2_pipe_clk", >> + "pcie30_phy3_pipe_clk", >> + "usb3phy_0_cc_pipe_clk"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + sdhc_1: mmc@7804000 { >> + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; >> + reg-names = "hc", "cqhci"; >> + >> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hc_irq", "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, >> + <&gcc GCC_SDCC1_APPS_CLK>, >> + <&xo_board_clk>; >> + clock-names = "iface", "core", "xo"; >> + non-removable; >> + status = "disabled"; >> + }; >> + >> + blsp1_uart2: serial@78b1000 { >> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; >> + reg = <0x078b1000 0x200>; >> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, >> + <&gcc GCC_BLSP1_AHB_CLK>; >> + clock-names = "core", "iface"; >> + status = "disabled"; >> + }; >> + >> + intc: interrupt-controller@b000000 { >> + compatible = "qcom,msm-qgic2"; >> + reg = <0x0b000000 0x1000>, /* GICD */ >> + <0x0b002000 0x1000>, /* GICC */ >> + <0x0b001000 0x1000>, /* GICH */ >> + <0x0b004000 0x1000>; /* GICV */ >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + ranges = <0 0x0b00c000 0x3000>; >> + >> + v2m0: v2m@0 { >> + compatible = "arm,gic-v2m-frame"; >> + reg = <0x00000000 0xffd>; >> + msi-controller; >> + }; >> + >> + v2m1: v2m@1000 { >> + compatible = "arm,gic-v2m-frame"; >> + reg = <0x00001000 0xffd>; >> + msi-controller; >> + }; >> + >> + v2m2: v2m@2000 { >> + compatible = "arm,gic-v2m-frame"; >> + reg = <0x00002000 0xffd>; >> + msi-controller; >> + }; >> + }; >> + >> + timer@b120000 { >> + compatible = "arm,armv7-timer-mem"; >> + reg = <0x0b120000 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + frame@b120000 { >> + reg = <0x0b121000 0x1000>, >> + <0x0b122000 0x1000>; >> + frame-number = <0>; >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + frame@b123000 { >> + reg = <0x0b123000 0x1000>; >> + frame-number = <1>; >> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + frame@b124000 { >> + reg = <0x0b124000 0x1000>; >> + frame-number = <2>; >> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + frame@b125000 { >> + reg = <0x0b125000 0x1000>; >> + frame-number = <3>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + frame@b126000 { >> + reg = <0x0b126000 0x1000>; >> + frame-number = <4>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + frame@b127000 { >> + reg = <0x0b127000 0x1000>; >> + frame-number = <5>; >> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + >> + frame@b128000 { >> + reg = <0x0b128000 0x1000>; >> + frame-number = <6>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> + }; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | >> IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | >> IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | >> IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | >> IRQ_TYPE_LEVEL_LOW)>; >> + }; >> +}; Best Regards, Devi Priya
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 557d77d48dc8..562952c76f7a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts new file mode 100644 index 000000000000..2c8430197ec0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 AL02-C7 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <384000000>; + bus-width = <8>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio10"; + function = "sdc_rclk"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi new file mode 100644 index 000000000000..2b86ba17bb32 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 SoC device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h> + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { + compatible = "fixed-clock"; + clock-frequency = <353000000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_region: tz@4a600000 { + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9574-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 65>; + interrupt-controller; + #interrupt-cells = <2>; + + uart2_pins: uart2-state { + pins = "gpio34", "gpio35"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq9574-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&bias_pll_ubi_nc_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "bias_pll_ubi_nc_clk", + "pcie30_phy0_pipe_clk", + "pcie30_phy1_pipe_clk", + "pcie30_phy2_pipe_clk", + "pcie30_phy3_pipe_clk", + "usb3phy_0_cc_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board_clk>; + clock-names = "iface", "core", "xo"; + non-removable; + status = "disabled"; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x1000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x1000>; /* GICV */ + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +};