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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id hu21-20020a05600ca29500b003eaee9e0d22sm12986242wmb.33.2023.03.07.05.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:18:15 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 14:17:43 +0100 Subject: [PATCH v2 14/18] arm64: dts: mediatek: add ethernet support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v2-14-6ec7cdb10ccf@baylibre.com> References: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> In-Reply-To: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> To: =?unknown-8bit?q?Zhiyong_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_Gue?= =?unknown-8bit?q?nter_Roeck_=3Clinux=40roeck-us=2Enet=3E=2C_Linus_Walleij_?= =?unknown-8bit?q?=3Clinus=2Ewalleij=40linaro=2Eorg=3E=2C?= =?unknown-8bit?q?_Bernhard_Rosenkr=C3=A4nzer_=3Cbero=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?AngeloGioacchino_Del_Regno_=3Cangelogioacchino=2Edelregno?= =?unknown-8bit?q?=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_Ulf_Hansson_=3Culf=2Ehansson=40linaro=2Eorg=3E=2C_Wim_Van_?= =?unknown-8bit?q?Sebroeck_=3Cwim=40linux-watchdog=2Eorg=3E=2C?= =?unknown-8bit?q?_Krzysztof_Kozlowski_=3Ckrzysztof=2Ekozlowski+dt=40linaro?= =?unknown-8bit?q?=2Eorg=3E=2C_Chaotian_Jing_=3Cchaotian=2Ejing=40mediatek?= =?unknown-8bit?q?=2Ecom=3E=2C?= =?unknown-8bit?q?_Rob_Herring_=3Crobh+dt=40kernel=2Eorg=3E=2C_Wenbin_Mei_=3C?= =?unknown-8bit?q?wenbin=2Emei=40mediatek=2Ecom=3E=2C_Matthias_Brugger_=3Cma?= =?unknown-8bit?q?tthias=2Ebgg=40gmail=2Ecom=3E?= Cc: linux-mmc@vger.kernel.org, Alexandre Bailon , devicetree@vger.kernel.org, Amjad Ouled-Ameur , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, Alexandre Mergnat , linux-mediatek@lists.infradead.org, Fabien Parent X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2433; i=amergnat@baylibre.com; h=from:subject:message-id; bh=Tf5+10DbTH8JmWbl0F1BhURJNU0ijmIE+qOre9BoIzg=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzmF/sAhqWjUqlEjJxepXUShC/SRz4SMSPGgs8dc 8Y4hC5qJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAc5hQAKCRArRkmdfjHURYrNEA C7FKCe06Tg3Xme8I9oeXAXAoQPa/GtIYgVzAnKYh8IYPyu/sjV1POXjfi2nmaSkHupKfhC6R0T2+Sp D6DwqRzHGwmVQlO3KzXiY2FjTBJEv8YbjiGNMdtfBhFKR2uvkKmugRENznoWO3joVv6M3Xjzk9ZjUP +MNSljha6j/IgWjT6UVeJmOQM8v6hHAuiOqttsrR5zwyCg5wtpCp05bcRDeyIvLJnKGJVglkdu09mm 7vOTsUpvszwFG+sEkijxxCPmhGcM6uqxIs/cdsnInOlgz4MGkF+S88eLc+MUFY1ss7AhhIWCx8t8og VbnKLRI6df/8HfIaMAfhZCyA1wzrUIRkPWiO4iSYu/y8oGTQqBQW1nBY+5i4LYwaznCV6Jccbhc5kP FksNuR3D9SRQRJTNkPHb0Din5Tqag8K1GzY1asD1IaK1qsMXyxH8uFkHiGWUw8Nl1Ptl5DKVnd5Afn bzWgZHA9MPLBnS13N32jkit1bvE0h4Qeo+cTO5czH8BB2BqQYzR/KBGCTPPalaR7ufapYP2mBKimU8 MJrKDx1uwmlWHYSrp2uI37SgGrdZ63hXOhtokvakvxUlMh8BWW+nu0+4wLsHkSj3O10fLPumy4SNSA pL7/MLDWW68rw9qikXp8l/oBuJCESSj43uffFxrd93bef/tvrhsZ48aF93Jw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230307_051816_433991_70283D8C X-CRM114-Status: GOOD ( 13.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - Enable "vibr" and "vsim2" regulators to power the ethernet chip. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 57 +++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 868ee0d160e4..1820daad6da3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,28 @@ optee_reserved: optee@43200000 { }; }; +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -140,12 +162,47 @@ &mt6357_pmic { #interrupt-cells = <2>; }; +/* Needed by analog switch (multiplexer), HDMI and ethernet */ +&mt6357_vibr_reg { + regulator-always-on; +}; + /* Needed by MSDC1 */ &mt6357_vmc_reg { regulator-always-on; }; +/* Needed by ethernet */ +&mt6357_vsim2_reg { + regulator-always-on; +}; + &pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = ; + }; + + rmii_pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gpio_keys: gpio-keys-pins { pins { pinmux = ;