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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id hu21-20020a05600ca29500b003eaee9e0d22sm12986242wmb.33.2023.03.07.05.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:18:07 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 14:17:37 +0100 Subject: [PATCH v2 08/18] arm64: dts: mediatek: add mt6357 PMIC support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v2-8-6ec7cdb10ccf@baylibre.com> References: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> In-Reply-To: <20230203-evk-board-support-v2-0-6ec7cdb10ccf@baylibre.com> To: =?unknown-8bit?q?Zhiyong_Tao_=3Czhiyong=2Etao=40mediatek=2Ecom=3E=2C_Gue?= =?unknown-8bit?q?nter_Roeck_=3Clinux=40roeck-us=2Enet=3E=2C_Linus_Walleij_?= =?unknown-8bit?q?=3Clinus=2Ewalleij=40linaro=2Eorg=3E=2C?= =?unknown-8bit?q?_Bernhard_Rosenkr=C3=A4nzer_=3Cbero=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?AngeloGioacchino_Del_Regno_=3Cangelogioacchino=2Edelregno?= =?unknown-8bit?q?=40collabora=2Ecom=3E=2C?= =?unknown-8bit?q?_Ulf_Hansson_=3Culf=2Ehansson=40linaro=2Eorg=3E=2C_Wim_Van_?= =?unknown-8bit?q?Sebroeck_=3Cwim=40linux-watchdog=2Eorg=3E=2C?= =?unknown-8bit?q?_Krzysztof_Kozlowski_=3Ckrzysztof=2Ekozlowski+dt=40linaro?= =?unknown-8bit?q?=2Eorg=3E=2C_Chaotian_Jing_=3Cchaotian=2Ejing=40mediatek?= =?unknown-8bit?q?=2Ecom=3E=2C?= =?unknown-8bit?q?_Rob_Herring_=3Crobh+dt=40kernel=2Eorg=3E=2C_Wenbin_Mei_=3C?= =?unknown-8bit?q?wenbin=2Emei=40mediatek=2Ecom=3E=2C_Matthias_Brugger_=3Cma?= =?unknown-8bit?q?tthias=2Ebgg=40gmail=2Ecom=3E?= Cc: linux-mmc@vger.kernel.org, Alexandre Bailon , devicetree@vger.kernel.org, Amjad Ouled-Ameur , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, Alexandre Mergnat , linux-mediatek@lists.infradead.org, Fabien Parent X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=984; i=amergnat@baylibre.com; h=from:subject:message-id; bh=FPhX0yoQh3im80vWPS01XYLfyse5M8tj6Tuzb4ULZNE=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzmEa9lzs4BtOFBFWSpzYa6jzRdhjauHPpgIr9E+ LV9xLHuJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAc5hAAKCRArRkmdfjHURcc2D/ 0f7dOlHW23au2uJsZ1Cpq1/33VxmdGsCv3qwIbPuufUaUiBDUVso+sx/ZuMen7To8zZ+M0m+tCvTUI N3rd7O1EscEe5IlWlAA31f4XMVuQQWTXutCm7I4FXk9nRxCQgHgoxxAE24vBdknmky4VCQ918RmTMr QQvJJjTz8Z0+Mc1vca/pYSksfa+UvujzOlI2Nf5FyADv7wB/kR9VRHrLSnf/5DwWa5ChWFIG+IfZ+R MQTwU1Sbqd3k+i61gWiB+L3YQPxxHZt6GYXopYNH+RaW7LZgYa2LyIbubabIcRkomxzlE/98Xamoq8 wgAITZHgJIkGDjlGZeCRMzEzAFaZbSKO/0Q41ZbIuVUEp8sRhAQaXkTfQBKKPS1RdcxtsGcTJ0QP2j wwDJAHYlskHQTUWHmyDjFe3LT0Lizex17S6kXEApgAA90SQc/FspNpBpi/4mjq8VXz1j5KO72lWwIk LALOnigx88FQatnwvQwUGGF6wwS0uXiGD+YTZwZIYb5tqGyII2lzIplD3hfOPWgEQ2lVRE7HG8JgHE UAzlI6rE+OsWJcxI0FuBpq+ZJuNDK7PdH2W9l7eYBSNMFB5aDIR72itEzWCu3OQiTwFgsfMYgXOL8I fHHggDAQMnsDefPj/o9FnrjVWyDwKS2rt1LRfCbEpu4wCpMoit1MRpeT5Z6A== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230307_131810_668534_058A6876 X-CRM114-Status: GOOD ( 11.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This power management system chip integration helps to manage regulators and keys. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index fc7f6d8ae173..2f88562c638a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -12,6 +12,7 @@ #include #include #include "mt8365.dtsi" +#include "mt6357.dtsi" / { model = "MediaTek MT8365 Open Platform EVK"; @@ -96,6 +97,13 @@ &i2c0 { #size-cells = <0>; }; +&mt6357_pmic { + interrupt-parent = <&pio>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; +}; + &pio { gpio_keys: gpio-keys-pins { pins {