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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id a18-20020a5d4d52000000b002d1e49cff35sm29667158wru.40.2023.03.29.02.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 02:52:36 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 29 Mar 2023 11:52:24 +0200 Subject: [PATCH RESEND 5/6] arm64: dts: mediatek: add larb support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230207-iommu-support-v1-5-4a902f9aa412@baylibre.com> References: <20230207-iommu-support-v1-0-4a902f9aa412@baylibre.com> In-Reply-To: <20230207-iommu-support-v1-0-4a902f9aa412@baylibre.com> To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Matthias Brugger , AngeloGioacchino Del Regno , Krzysztof Kozlowski Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2836; i=amergnat@baylibre.com; h=from:subject:message-id; bh=XjVkw1GDKMmeBhzbo3W1bEYNyW+ZnWm1iMDrvQExCYA=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkJApf/0xy8f4tuG475vEqLpUT9xY0KkdHZQQ16mEE UQPiw+aJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCQKXwAKCRArRkmdfjHURXdwD/ sF3luANvTX/Sa5VyhmA9Hasmqiwa6puy5j3JQ79X/9L/KmyFAFND/Bgphp6AMuEviGaRVPdgR+9hye 1jXJqcsaF6eIDmuBGRxGJOsNzUy8Pv5jMOEtrFFgD3dmS3UWsjGyEjU4RQqz9uDTa28p7GB0TPErz3 uaMUbhJfpvgYY0zNidXInfXirOkPNyBspyhlTGRJjRqFMIKwZM+4HKZe58AIOA4OeYNQP38ZrOncgD 01ML1FkhJrFPDV106REYQw5K2G03GxbKD4nOGXuDLJT3mAlSiV+rWB/S+L+loKmBZWI6NLwsLfouQI W5rAPb6vWFHY77ZxYsVfQnMFhXrBJrUTWu1r2If/J5BA90Jg3qtRXlj/nlaalx5gkQdxnre8A/inl9 D8wYmODOQ9O5v1UgCkYcopTm2Ao5B6f8adc7zD3FZ4OCfhQeN9SDcGPDLrMnpOM3mYmXZuwjubI7+g Yn2Ul0EelA6lw9TwpFMvI/+psr59bePCoyubIcTB+DrK5TshHrRoWcuv6nuZrROQTkVaUNaHE2E7MH pjUsbKXjQ7ndRHSPRaKOW26JAyVAu9O/U7jeMBcEWt4MYCQYLmxAbqh3CaDtsCmoorEiXqdcClX3XU Dg2AFjmeizRd2PIoIJVTqEoJbYD8Ku36OAiuUpE80pnALRXjkH5CmvHQ9W3Q== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230329_105239_151613_8085FE09 X-CRM114-Status: GOOD ( 11.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Local arbiter (LARB) is a component of Smart Multimedia Interface (SMI), used to help the memory management (IOMMU). This patch add 4 LARBs and 2 clocks for the larb1 and larb3 support. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 59 ++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 61333800ff4a..db0b897f58bb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -725,12 +725,71 @@ smi_common: smi@14002000 { power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; + larb0: larb@14003000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + mediatek,larb-id = <0>; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@15001000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB2>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + mediatek,larb-id = <2>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8365-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@16010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; + mediatek,larb-id = <3>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8365-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@17010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; + mediatek,larb-id = <1>; + }; + apu: syscon@19020000 { compatible = "mediatek,mt8365-apu", "syscon"; reg = <0 0x19020000 0 0x1000>;