From patchwork Sat Feb 11 03:15:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13136835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55043C05027 for ; Sat, 11 Feb 2023 03:19:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=jqNrRusSFkfMpB7EbfFqlsL8wMtKntcJAZ9VsB4NMSg=; b=zw91Ln41QoLk+s+A7wNA/nLZKc eB43vqAyXERU65ZVSAspo4O3nzRcZcdhcX/3fzWPBu+OdMI15IpjeG5p9Z6MWtdC8Y6MyvasQUaAk UIiRqLGmm3smNv6U6UbnNyTxG3scgtxUEpPOKRL4sA+PCgB1iqFcRUNbjBARDqboEicX3zJ5uoaTm 3ajdGDuRe/JvCOtZ8eYIosMlmlG2CLyC5xU4dfHqJC1Nx064fvvlhcFdeEhzVqlIuXr33i/VOnDHP b8cZBvlWqgivMeujnZKB707AzqkGOsWUkMN+apSVlZHagGrQ7jyvmILA1eiFU68lQw04f8LLE1avr Rvrd6U7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQgP7-008Ra6-9a; Sat, 11 Feb 2023 03:18:22 +0000 Received: from mail-yb1-xb49.google.com ([2607:f8b0:4864:20::b49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQgNf-008Qrp-0o for linux-arm-kernel@lists.infradead.org; Sat, 11 Feb 2023 03:16:52 +0000 Received: by mail-yb1-xb49.google.com with SMTP id 200-20020a2505d1000000b0088347752c5fso6742285ybf.18 for ; Fri, 10 Feb 2023 19:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=GkyY7Gx/s8/i/TTD/6iIAVcAbXfz7PChndlkN6KcDWs=; b=aWCxlbutS6tvx8ncRgPUNTg+LVzebZ1TcLsZxcBSxShSo03wp7fKLrArqZLzMdxZys DO8mf9PdL/hZ7JFCSICilphiRaxR3c6JlqdJ8bP3dZORlTV04KW/aSO0lqTh1SjMS4tD 5wHDaOagoNYvde9C1vA4KMFTFLnZ7IXl/V1pxvVH4iZG+ySBN+Y67MnhBW661eh3LzTB DkCMPrW3bTZXfamUKqawUlyzRUKN75i1vUE6eVs8ASsoVa2P/1rUch4MPbEe3g0QVuev V/LmN1kHy+vQ0EiLlOPacse0QRWmQRlH62H/ys4htod44MA5bitDXdeuQj3LByMLQCjp 7ADg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GkyY7Gx/s8/i/TTD/6iIAVcAbXfz7PChndlkN6KcDWs=; b=GCWT3T+W9Ty/xl4Jh3BcGWva28VTOT/DmXc3ZrCO5hacgcabsHDSIrqvJwtPQCKTj7 e9hldRG3O9vSMmRJXnuc4pj4d23E0uJCJHXVihkfgZ5b++bdDQcOoU0HyA9nS5KEvmjX PP9jrp0UXerUYghq0OqK8Kl+03vfshcTbTXSwecvVEvz5Q+rxT8jcRNiw1gHICl/b5wN gJKf1jsswSwm8+6vi+fUtP3WcmB9WmbGYe5h0ZW5o2IqOZSWbrZbv+c3F0T4Q4ggU7ma gDEmbtNRqgrsA+89iQo11gILJvEMM8zG5MCRm5rGjxzpKlo+fqqHS7LyQrvGkY/DBwpy OOZA== X-Gm-Message-State: AO0yUKXjllfeBQMqC0pAZ70e92bpJHmp6/QYlFEGcLpWUVJY2hs/IHuc 8n+AQGjk9SLrUoJUt4jCOYFZwRJQBlk= X-Google-Smtp-Source: AK7set9TyxqyB3MrEE0xni9aCszn1JDl4djoMf7oBNVJBOZaZF/s+PPLMNvAAkPhEZEamhabR+JIQEZKZHA= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a81:5e43:0:b0:4e3:f87:8c24 with SMTP id s64-20020a815e43000000b004e30f878c24mr2050846ywb.248.1676085409706; Fri, 10 Feb 2023 19:16:49 -0800 (PST) Date: Fri, 10 Feb 2023 19:15:01 -0800 In-Reply-To: <20230211031506.4159098-1-reijiw@google.com> Mime-Version: 1.0 References: <20230211031506.4159098-1-reijiw@google.com> X-Mailer: git-send-email 2.39.1.581.gbfd45094c4-goog Message-ID: <20230211031506.4159098-10-reijiw@google.com> Subject: [PATCH v4 09/14] KVM: arm64: PMU: Set PMCR_EL0.N for vCPU based on the associated PMU From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230210_191651_098745_0CB292BE X-CRM114-Status: GOOD ( 20.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The number of PMU event counters is indicated in PMCR_EL0.N. For a vCPU with PMUv3 configured, the value is set to the same value as the current PE on every vCPU reset. Unless the vCPU is pinned to PEs that has the PMU associated to the guest from the initial vCPU reset, the value might be different from the PMU's PMCR_EL0.N on heterogeneous PMU systems. Fix this by setting the vCPU's PMCR_EL0.N to the PMU's PMCR_EL0.N value. Track the PMCR_EL0.N per guest, as only one PMU can be set for the guest (PMCR_EL0.N must be the same for all vCPUs of the guest), and it is convenient for updating the value. KVM does not yet support userspace modifying PMCR_EL0.N. The following patch will add support for that. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/pmu-emul.c | 14 +++++++++++++- arch/arm64/kvm/sys_regs.c | 17 ++++++++++------- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 33839077a95c..734f1b6f7468 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -233,6 +233,9 @@ struct kvm_arch { u8 imp_limit; } dfr0_pmuver; + /* PMCR_EL0.N value for the guest */ + u8 pmcr_n; + /* Hypercall features firmware registers' descriptor */ struct kvm_smccc_features smccc_feat; diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 5ff44224148f..3053c06db7a9 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -680,6 +680,9 @@ void kvm_host_pmu_init(struct arm_pmu *pmu) if (!entry) goto out_unlock; + WARN_ON((pmu->num_events <= 0) && + (pmu->num_events > ARMV8_PMU_MAX_COUNTERS)); + entry->arm_pmu = pmu; list_add_tail(&entry->entry, &arm_pmus); @@ -881,6 +884,13 @@ int kvm_arm_set_vm_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu) kvm->arch.dfr0_pmuver.imp_limit = min_t(u8, arm_pmu->pmuver, ID_AA64DFR0_EL1_PMUVer_V3P5); kvm->arch.dfr0_pmuver.imp = kvm->arch.dfr0_pmuver.imp_limit; + /* + * Both the num_events and PMCR_EL0.N indicates the number of + * PMU event counters, but the former includes the cycle counter + * while the latter does not. + */ + kvm->arch.pmcr_n = arm_pmu->num_events - 1; + return 0; } @@ -1074,5 +1084,7 @@ u8 kvm_arm_pmu_get_pmuver_limit(void) u64 kvm_vcpu_read_pmcr(struct kvm_vcpu *vcpu) { - return __vcpu_sys_reg(vcpu, PMCR_EL0); + u64 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0) & ~ARMV8_PMU_PMCR_N; + + return pmcr | ((u64)vcpu->kvm->arch.pmcr_n << ARMV8_PMU_PMCR_N_SHIFT); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9f8c25e49a5a..aba93db29697 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -624,12 +624,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { u64 pmcr; - /* No PMU available, PMCR_EL0 may UNDEF... */ - if (!kvm_arm_support_pmu_v3()) - return; - /* Only preserve PMCR_EL0.N, and reset the rest to 0 */ - pmcr = read_sysreg(pmcr_el0) & ARMV8_PMU_PMCR_N; + pmcr = kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_N; if (!kvm_supports_32bit_el0()) pmcr |= ARMV8_PMU_PMCR_LC; @@ -946,6 +942,13 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, return true; } +static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, + u64 *val) +{ + *val = kvm_vcpu_read_pmcr(vcpu); + return 0; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ @@ -1719,8 +1722,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CTR_EL0), access_ctr }, { SYS_DESC(SYS_SVCR), undef_access }, - { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, - .reset = reset_pmcr, .reg = PMCR_EL0 }, + { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, + .reg = PMCR_EL0, .get_user = get_pmcr }, { PMU_SYS_REG(SYS_PMCNTENSET_EL0), .access = access_pmcnten, .reg = PMCNTENSET_EL0 }, { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),