From patchwork Sat Feb 11 03:14:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13136802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F62EC05027 for ; Sat, 11 Feb 2023 03:17:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=VZVoBkzhnW3RjVouhXInpinIimSbnpN88jtG+/Rnx4k=; b=2CdHpEuYYLVcgC/RPZ5WfSJs7s vmtwOHhA+XBVM0n4HnbshVmpBCuKvfLuy5nlZX8HRZhuvW/VwNPDIXuLHAow7RaAK2NSZzWI1YX4m 1UzXviWkV259QjJ62YOR5KcO2dQOB/8o3TenXBk0HAIbjnszRxDLtCmqaaVkUACMPkesG/X15bbeJ 8PgZBZokpj1O8Ga0hSwUh1Mz9hs3IswOoaCTaja6JBze5aOM9quOMuj0mmtLOJZkLCnDchCnFwlte ghyzhAebGWfxykVx7Ln0/wuTj4ShwadGFT4waPyitowsad9U+naw9hoDtS1lohNHOq+pEL/11DIs2 H13fIpkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQgNa-008Qpo-Vc; Sat, 11 Feb 2023 03:16:47 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQgNW-008QmY-GC for linux-arm-kernel@lists.infradead.org; Sat, 11 Feb 2023 03:16:45 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-52ec2c6b694so53701527b3.19 for ; Fri, 10 Feb 2023 19:16:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=RBT5x66aj0o+bGVgZJhYwS6XmSzkSdatLkUK3qko77M=; b=ZSz6nXEHRKC94b0+dd0cJ2iN8ANusTD8u+RwkNdGXCMXNBFQhzC6Vbt9PFrPwbX48w 6tclEBudcfYEoIbh1fF64f8HSG8PqMV78j4ulFdqk26qpVr90D4xfdOuav5C0/N5PteN GiVdCAnseLwKcGY0r0zUZ2GD/FgzgPiwjXol1mD6QnU4t6qSt+3R2V2TGVq+/lzXJKa3 uGWhkat/VK1TI23yfMziDsa6XpvhT5rcPoC+S3tgpq8N2MX/f5xaf87kYqSX9kyKvlbv 6OyXYVVw7i0q3mI5imrYK/nTYz9PYMDSBpgMTU0nrdRRZ2ji9h4ypJPlrBVlIuiW68bB nhxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=RBT5x66aj0o+bGVgZJhYwS6XmSzkSdatLkUK3qko77M=; b=UCZM+YmKm4G9QDVtG0ZTQ03NaokK+nAB4bQD+JZuh/CJnBbi+N28q2Szb6zaO0Djnd o7wpTE+hRrHJvlqQCseG5AFU1AmJLG9E6hdbyfkfGbD12XL96asQdJK0rQdGDbiwNrQm xPYydd+YR4/jgY7JgkvQlDXsIOOD69q1CeCahJGMzEDow18PH2Q9/+pcL5sMMqmvV3Qo 3L44dV+tBmcvUpReFtpI7p0mJ2YBkEgjfMrwaxqvH1JBs1u0BfxeKFqg3x2xjZA2rSJJ 95uRX/ormsAhycIRu7x/qx0UXHevVwNj85ij5qurMjO7SEE/vMmZfrqq87HryEZ5R5aq mNwA== X-Gm-Message-State: AO0yUKW8EsL3EdD5E/zAv8CZgVuCCCtQ78dQ4cGH7TEc6pXBrABhT+Ql PceuPAax/ZZY1zNmGP1MKosNZk9B/10= X-Google-Smtp-Source: AK7set9PagVjhSsFZquxxbL9a5MP6qEOSBD/vZTrtrlmS9TLAckHrNrA532H7ANzqpZDfdckSdHc7xqLCoQ= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a25:dccc:0:b0:8dc:e5aa:b60 with SMTP id y195-20020a25dccc000000b008dce5aa0b60mr6ybe.12.1676085400111; Fri, 10 Feb 2023 19:16:40 -0800 (PST) Date: Fri, 10 Feb 2023 19:14:56 -0800 In-Reply-To: <20230211031506.4159098-1-reijiw@google.com> Mime-Version: 1.0 References: <20230211031506.4159098-1-reijiw@google.com> X-Mailer: git-send-email 2.39.1.581.gbfd45094c4-goog Message-ID: <20230211031506.4159098-5-reijiw@google.com> Subject: [PATCH v4 04/14] KVM: arm64: PMU: Don't use the PMUVer of the PMU set for the guest From: Reiji Watanabe To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230210_191642_562997_96F30D19 X-CRM114-Status: GOOD ( 16.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM uses two potentially different PMUVer for a vCPU with PMU configured (kvm->arch.dfr0_pmuver.imp and kvm->arch.arm_pmu->pmuver). Stop using the host's PMUVer (arm_pmu->pmuver) in most cases, as the PMUVer for the guest (kvm->arch.dfr0_pmuver.imp) could be set by userspace (could be lower than the host's PMUVer). The only exception to KVM using the host's PMUVer is to create an event filter (KVM_ARM_VCPU_PMU_V3_FILTER). For this, KVM uses the value to determine the valid range of the event, and as the size of the event filter bitmap. Using the host's PMUVer here will allow KVM to keep the compatibility with the current behavior of the PMU_V3_FILTER. Also, that will allow KVM to keep the entire filter when PMUVer for the guest is changed, and KVM only need to change the actual range of use. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/pmu-emul.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 49580787ee09..701728ad78d6 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -35,12 +35,8 @@ static struct kvm_pmc *kvm_vcpu_idx_to_pmc(struct kvm_vcpu *vcpu, int cnt_idx) return &vcpu->arch.pmu.pmc[cnt_idx]; } -static u32 kvm_pmu_event_mask(struct kvm *kvm) +static u32 __kvm_pmu_event_mask(u8 pmuver) { - unsigned int pmuver; - - pmuver = kvm->arch.arm_pmu->pmuver; - switch (pmuver) { case ID_AA64DFR0_EL1_PMUVer_IMP: return GENMASK(9, 0); @@ -55,6 +51,11 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) } } +static u32 kvm_pmu_event_mask(struct kvm *kvm) +{ + return __kvm_pmu_event_mask(kvm->arch.dfr0_pmuver.imp); +} + /** * kvm_pmc_is_64bit - determine if counter is 64bit * @pmc: counter context @@ -755,7 +756,7 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled * as RAZ */ - if (vcpu->kvm->arch.arm_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4) + if (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P4) val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); base = 32; } @@ -955,7 +956,12 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) struct kvm_pmu_event_filter filter; int nr_events; - nr_events = kvm_pmu_event_mask(kvm) + 1; + /* + * Allocate an event filter for the entire range supported + * by the PMU hardware so we can simply change the actual + * range of use when the PMUVer for the guest is changed. + */ + nr_events = __kvm_pmu_event_mask(kvm->arch.dfr0_pmuver.imp_limit) + 1; uaddr = (struct kvm_pmu_event_filter __user *)(long)attr->addr;