From patchwork Tue Feb 14 14:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 303C4C61DA4 for ; Tue, 14 Feb 2023 14:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TX8/6JlPnRW6Eymi92xP6uBct1ZHGVsFJuoFKKmZioE=; b=47mDoMssyFoBVj owbx5pHMw9qGjUF7+9jipEaP21AoUgfFQC/ahmmSQ8hGLt6F4BH/0zTN/KUPSluPSp2EYCzOR7+l8 mC4Mf+S6iY95GMw3XISLNTzW5CjhzLwBjTbeFNgZ7JiQD/zomHhgWj9mOKQMif4rSoHGDA33i4yim Ui1qRf3O394Tb+oS72jz9gZoTvLtDQERUgv/nlC3CwM8KstQE5E3V7T09vXyu6Vpay7SqQSzXK5Gu esNdrCe8frLSCFLQuawYzChvU53Ll2ExmoRNISo+ibJDpvY/0+DtV/5hd3OP+V/sO1wH9sCmG/uM+ lPWe39BYiZm0R2bp4a7w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pRwZ5-002H15-QK; Tue, 14 Feb 2023 14:45:52 +0000 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pRw0b-0021PC-7J; Tue, 14 Feb 2023 14:10:14 +0000 Received: by mail-ej1-x62e.google.com with SMTP id lf10so8514959ejc.5; Tue, 14 Feb 2023 06:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G4b0gzVsxfEDBk+JDTdDvkxVPx/flrfnXIUXp8EED98=; b=nxK2vZfJXOqwBGbbppTW8iDiFJSXqmQ5KmohCvhBk0pjaSYsqYIoB4TI4NRG7P0IkW 7d1QUkfthIZN1ya1+OMz3yiVYsupijkwSRdTDvZtWpdqKoFywte3fNHQNFs5jnoxUg5t 5O7Vc5L75Fg2Vs/gVnmtr1U/usiZ1xPuaAk2SErDZi1Jks3kCTJcEUyBeZrhtfw9np1H 0SYt8QFz6840QrA0K8YZiGVnBNhebtlcqRwZ0Bu7wywZvz/empEeN/tbNVsL8zNJLrH7 12U5um6OMZqb2jKJ+UrtiGggWUouIEZFPeYsrZRRt05z9MvWwlFWbRUupJAAbHrKwA4i 1KiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G4b0gzVsxfEDBk+JDTdDvkxVPx/flrfnXIUXp8EED98=; b=VtkocAZFGyac1WK5i11Azxol7qD5uecwbwiAgo2OrNckUcRZjYeIu4FH6E6NaubZqx YoK74AwYt71zUUpUh99RtzmZ0cP87EFY32o+IXhPCEKLSmrmPQ5iSCW6eSwKSesQHblk 9E9hKNzdo4GrbXE1GBTSSRbtLWh5KKaDJy4DQk+IJ4W/NSOXt3cqRkWgLO9DLLHC8yJf pVbWf7ESP+TCEd9PNjOKpGVKuSlhmk5WEmNblzCdYb4x1GY1yPt7Um8frETpP3Z9aebn mIhJm1uQWDD8mJEWBO9Uf8piDpCCBtL3DJDA+yOIBNN9mlHyUWU+fgDyQ8NXji203szM +j3w== X-Gm-Message-State: AO0yUKXlM4iw4gwt84oUk0mhGHylilgX+tZjiCcO168ZKMSV+ubKgxrn M817p5ljptlCsxflugxTXJ8= X-Google-Smtp-Source: AK7set+P3I5w7NnN9v0I+op7ljbZo1mpuW8lMzNNdJQ1kPpeO7OxY8oGIb+Y6liq++qmYYEvZIT26w== X-Received: by 2002:a17:906:b886:b0:8aa:be1a:c4bf with SMTP id hb6-20020a170906b88600b008aabe1ac4bfmr4165664ejb.16.1676383811928; Tue, 14 Feb 2023 06:10:11 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:11 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Mikko Kovanen , Rodrigo Vivi , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 7/9] PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core Date: Tue, 14 Feb 2023 15:08:55 +0100 Message-Id: <20230214140858.1133292-8-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230214_061013_311495_F4A3F7D4 X-CRM114-Status: GOOD ( 15.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Fix legacy IRQ generation for RK3399 PCIe endpoint core according to the technical reference manual (TRM). Assert and deassert legacy interrupt (INTx) through the legacy interrupt control register ("PCIE_CLIENT_LEGACY_INT_CTRL") instead of manually generating a PCIe message. The generation of the legacy interrupt was tested and validated with the PCIe endpoint test driver. Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 38 +++++------------------ drivers/pci/controller/pcie-rockchip.h | 6 ++++ 2 files changed, 14 insertions(+), 30 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index cbc281a6a..ca5b363ba 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -328,45 +328,23 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, u8 intx, bool is_asserted) { struct rockchip_pcie *rockchip = &ep->rockchip; - u32 r = ep->max_regions - 1; - u32 offset; - u32 status; - u8 msg_code; - - if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || - ep->irq_pci_fn != fn)) { - rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, - AXI_WRAPPER_NOR_MSG, - ep->irq_phys_addr, 0, 0); - ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; - ep->irq_pci_fn = fn; - } intx &= 3; if (is_asserted) { ep->irq_pending |= BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; } else { ep->irq_pending &= ~BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; } - status = rockchip_pcie_read(rockchip, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); - status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - - if ((status != 0) ^ (ep->irq_pending != 0)) { - status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - rockchip_pcie_write(rockchip, status, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); + if (is_asserted) { + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_ASSERT | PCIE_CLIENT_INT_PEND_ST_PEND, + PCIE_CLIENT_LEGACY_INT_CTRL); + } else { + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_DEASSERT | PCIE_CLIENT_INT_PEND_ST_NORMAL, + PCIE_CLIENT_LEGACY_INT_CTRL); } - - offset = - ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | - ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; - writel(0, ep->irq_cpu_addr + offset); } static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 72e427a0f..e90c2a2b8 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -39,6 +39,12 @@ #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) #define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) +#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) +#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) #define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)