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Tue, 07 Mar 2023 05:04:53 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.219]) by smtp.gmail.com with ESMTPSA id w14-20020ac2598e000000b004caf992bba9sm2030548lfn.268.2023.03.07.05.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:04:53 -0800 (PST) From: Linus Walleij Date: Tue, 07 Mar 2023 14:04:50 +0100 Subject: [PATCH v2 08/16] gpio: hlwd: Convert to immutable irq_chip MIME-Version: 1.0 Message-Id: <20230215-immutable-chips-v2-8-d6b0e3f2d991@linaro.org> References: <20230215-immutable-chips-v2-0-d6b0e3f2d991@linaro.org> In-Reply-To: <20230215-immutable-chips-v2-0-d6b0e3f2d991@linaro.org> To: Mun Yew Tham , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Alban Bedel , Orson Zhai , Baolin Wang , Chunyan Zhang , Jay Fang , Daniel Palmer , Romain Perier , Santosh Shilimkar , Kevin Hilman , William Breathitt Gray Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-omap@vger.kernel.org, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230307_050454_331847_B8961B99 X-CRM114-Status: GOOD ( 17.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Acked-by: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/gpio/gpio-hlwd.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-hlwd.c b/drivers/gpio/gpio-hlwd.c index 4e13e937f832..c208ac1c54a6 100644 --- a/drivers/gpio/gpio-hlwd.c +++ b/drivers/gpio/gpio-hlwd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include /* @@ -48,7 +49,7 @@ struct hlwd_gpio { struct gpio_chip gpioc; - struct irq_chip irqc; + struct device *dev; void __iomem *regs; int irq; u32 edge_emulation; @@ -123,6 +124,7 @@ static void hlwd_gpio_irq_mask(struct irq_data *data) mask &= ~BIT(data->hwirq); iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); + gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); } static void hlwd_gpio_irq_unmask(struct irq_data *data) @@ -132,6 +134,7 @@ static void hlwd_gpio_irq_unmask(struct irq_data *data) unsigned long flags; u32 mask; + gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); mask |= BIT(data->hwirq); @@ -202,6 +205,24 @@ static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) return 0; } +static void hlwd_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct hlwd_gpio *hlwd = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); + + seq_printf(p, dev_name(hlwd->dev)); +} + +static const struct irq_chip hlwd_gpio_irq_chip = { + .irq_mask = hlwd_gpio_irq_mask, + .irq_unmask = hlwd_gpio_irq_unmask, + .irq_enable = hlwd_gpio_irq_enable, + .irq_set_type = hlwd_gpio_irq_set_type, + .irq_print_chip = hlwd_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int hlwd_gpio_probe(struct platform_device *pdev) { struct hlwd_gpio *hlwd; @@ -216,6 +237,8 @@ static int hlwd_gpio_probe(struct platform_device *pdev) if (IS_ERR(hlwd->regs)) return PTR_ERR(hlwd->regs); + hlwd->dev = &pdev->dev; + /* * Claim all GPIOs using the OWNER register. This will not work on * systems where the AHBPROT memory firewall hasn't been configured to @@ -259,14 +282,8 @@ static int hlwd_gpio_probe(struct platform_device *pdev) return hlwd->irq; } - hlwd->irqc.name = dev_name(&pdev->dev); - hlwd->irqc.irq_mask = hlwd_gpio_irq_mask; - hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask; - hlwd->irqc.irq_enable = hlwd_gpio_irq_enable; - hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type; - girq = &hlwd->gpioc.irq; - girq->chip = &hlwd->irqc; + gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip); girq->parent_handler = hlwd_gpio_irqhandler; girq->num_parents = 1; girq->parents = devm_kcalloc(&pdev->dev, 1,