From patchwork Thu Feb 16 18:21:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13143659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F189C61DA4 for ; Thu, 16 Feb 2023 18:23:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DT86XPhAZDbJg83H3lXJNVoCItBz2gQpk1qtnvbRrVs=; b=ISK5Cxd9QBZ9RR dElURITH2e3E1XeUo2XJ/cxZx+yPxVm1xLmyz2eWlGpTBCH22GbWTPMqeTaBPtncD4DCGVe5wpRLT SvOZiirVgGyNmrh5YJBAptOSFe9ed6aMy8cHR/d1eHEudq4BPMzP1/sxwTh/2luzkCdezZlrOvzaE Nu1yPnatO5FDVLX8YfFR6EXoe087s0w1ptXf+s34EmnxRSQR9XLmGP5NZB+6S2MBVC3y5fOAbOcea d8umlcGfIbb2c7Zx2PRVQlk0wywYiCXy+Zai2NAxKVdcAKYZ85URdASjgbhaI8C/AWHMzUNfRXdnQ ew+GKhiCSZke4l9X8diA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSiuJ-00BUok-VX; Thu, 16 Feb 2023 18:23:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSitn-00BURr-Nt for linux-arm-kernel@lists.infradead.org; Thu, 16 Feb 2023 18:22:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 421F91042; Thu, 16 Feb 2023 10:23:08 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 563FB3F663; Thu, 16 Feb 2023 10:22:24 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse Subject: [RFC PATCH 1/3] firmware: smccc: Add support for erratum discovery API Date: Thu, 16 Feb 2023 18:21:59 +0000 Message-Id: <20230216182201.1705406-2-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230216182201.1705406-1-james.morse@arm.com> References: <20230216182201.1705406-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230216_102227_916914_6849571D X-CRM114-Status: GOOD ( 21.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It is not always possible for the OS to determine if a CPU is affected by a particular erratum. For example, it may depend on an integration choice the chip designer made, or whether firmware has enabled some particular feature. Add support for the SMCCC 'Errata Management Firmware Interface' that lets the OS query firmware for this information. Link: https://developer.arm.com/documentation/den0100/1-0/?lang=en Signed-off-by: James Morse --- arch/arm64/kernel/cpufeature.c | 6 +++ drivers/firmware/smccc/Kconfig | 8 ++++ drivers/firmware/smccc/Makefile | 1 + drivers/firmware/smccc/em.c | 78 +++++++++++++++++++++++++++++++++ include/linux/arm-smccc.h | 28 ++++++++++++ 5 files changed, 121 insertions(+) create mode 100644 drivers/firmware/smccc/em.c diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a77315b338e6..2eb4d38e491a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -62,6 +62,7 @@ #define pr_fmt(fmt) "CPU features: " fmt +#include #include #include #include @@ -1036,6 +1037,11 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) */ init_cpu_hwcaps_indirect_list(); + /* + * Early erratum workaround may need to be discovered from firmware. + */ + arm_smccc_em_init(); + /* * Detect and enable early CPU capabilities based on the boot CPU, * after we have initialised the CPU feature infrastructure. diff --git a/drivers/firmware/smccc/Kconfig b/drivers/firmware/smccc/Kconfig index 15e7466179a6..a10a150d49bb 100644 --- a/drivers/firmware/smccc/Kconfig +++ b/drivers/firmware/smccc/Kconfig @@ -23,3 +23,11 @@ config ARM_SMCCC_SOC_ID help Include support for the SoC bus on the ARM SMCCC firmware based platforms providing some sysfs information about the SoC variant. + +config ARM_SMCCC_EM + bool "Errata discovery by ARM SMCCC" + depends on HAVE_ARM_SMCCC_DISCOVERY + default y + help + Include support for querying firmware via SMCCC to determine whether + the CPU is affected by a specific erratum. diff --git a/drivers/firmware/smccc/Makefile b/drivers/firmware/smccc/Makefile index 40d19144a860..39ed128b59b5 100644 --- a/drivers/firmware/smccc/Makefile +++ b/drivers/firmware/smccc/Makefile @@ -2,3 +2,4 @@ # obj-$(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) += smccc.o kvm_guest.o obj-$(CONFIG_ARM_SMCCC_SOC_ID) += soc_id.o +obj-$(CONFIG_ARM_SMCCC_EM) += em.o diff --git a/drivers/firmware/smccc/em.c b/drivers/firmware/smccc/em.c new file mode 100644 index 000000000000..2c66240d8707 --- /dev/null +++ b/drivers/firmware/smccc/em.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Arm Errata Management firmware interface. + * + * This firmware interface advertises support for firmware mitigations for CPU + * errata. It can also be used to discover erratum where the 'configurations + * affected' depends on the integration. + * + * Copyright (C) 2022 ARM Limited + */ + +#define pr_fmt(fmt) "arm_smccc_em: " fmt + +#include +#include +#include +#include + +#include + +#include + +static u32 supported; + +int arm_smccc_em_cpu_features(u32 erratum_id) +{ + struct arm_smccc_res res; + + if (!READ_ONCE(supported)) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_CPU_ERRATUM_FEATURES, erratum_id, 0, &res); + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_EM_RET_INVALID_PARAMTER: + return -EINVAL; + case SMCCC_EM_RET_UNKNOWN: + return -ENOENT; + case SMCCC_EM_RET_HIGHER_EL_MITIGATION: + case SMCCC_EM_RET_NOT_AFFECTED: + case SMCCC_EM_RET_AFFECTED: + return res.a0; + }; + + return -EIO; +} + +int __init arm_smccc_em_init(void) +{ + u32 major_ver, minor_ver; + struct arm_smccc_res res; + enum arm_smccc_conduit conduit = arm_smccc_1_1_get_conduit(); + + if (conduit == SMCCC_CONDUIT_NONE) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_VERSION, &res); + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) + return -EOPNOTSUPP; + + major_ver = PSCI_VERSION_MAJOR(res.a0); + minor_ver = PSCI_VERSION_MINOR(res.a0); + if (major_ver != 1) + return -EIO; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_FEATURES, + ARM_SMCCC_EM_CPU_ERRATUM_FEATURES, &res); + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) + return -EOPNOTSUPP; + + pr_info("SMCCC Errata Management Interface v%d.%d\n", + major_ver, minor_ver); + + WRITE_ONCE(supported, 1); + + return 0; +} diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 220c8c60e021..cc2e38ce8707 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -182,6 +182,25 @@ ARM_SMCCC_OWNER_STANDARD, \ 0x53) +/* Errata Management calls (defined by ARM DEN0100) */ +#define ARM_SMCCC_EM_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF0) + +#define ARM_SMCCC_EM_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF1) + +#define ARM_SMCCC_EM_CPU_ERRATUM_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF2) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C @@ -191,6 +210,15 @@ #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +/* + * Return codes defined in ARM DEN 0100 + */ +#define SMCCC_EM_RET_HIGHER_EL_MITIGATION 3 +#define SMCCC_EM_RET_NOT_AFFECTED 2 +#define SMCCC_EM_RET_AFFECTED 1 +#define SMCCC_EM_RET_INVALID_PARAMTER -2 +#define SMCCC_EM_RET_UNKNOWN -3 + #ifndef __ASSEMBLY__ #include