| Message ID | 20230221105039.316819-2-robert.marko@sartura.hr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/3] arm64: dts: microchip: sparx5: do not use PSCI on reference boards | expand |
On 21/02/2023 11:50, Robert Marko wrote: > There is no reason for CPU node #address-cells to be set at 2, so lets > change them to 1 and update the reg property accordingly. > > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > --- > arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > Patch seemed forgotten, so I applied it. https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git/log/?h=next/dt64 Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 5eae6e7fd248e..a4fabacf5c2f7 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -24,7 +24,7 @@ chosen { }; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { @@ -39,14 +39,14 @@ core1 { cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x0>; + reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x1>; + reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; };
There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly. Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)