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Sat, 25 Feb 2023 02:17:15 -0800 (PST) Received: from localhost.localdomain ([95.183.227.97]) by smtp.gmail.com with ESMTPSA id y23-20020a50ce17000000b004af6163f845sm677722edi.28.2023.02.25.02.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 02:17:14 -0800 (PST) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 3/3] soc: mediatek: scpsys: Add support for MT6735 Date: Sat, 25 Feb 2023 13:16:29 +0300 Message-Id: <20230225101629.264206-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230225101629.264206-1-y.oudjana@protonmail.com> References: <20230225101629.264206-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230225_021722_188482_50E40311 X-CRM114-Status: GOOD ( 14.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yassine Oudjana Add support for SCPSYS power domains of MT6735. All non-CPU power domains are added except for MD2 (C2K modem), which is left out due to issues with powering it on. Signed-off-by: Yassine Oudjana --- drivers/soc/mediatek/mtk-scpsys.c | 84 +++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 7a668888111c..b771bfb93cc9 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -32,6 +33,7 @@ #define SPM_VEN_PWR_CON 0x0230 #define SPM_ISP_PWR_CON 0x0238 #define SPM_DIS_PWR_CON 0x023c +#define SPM_MD1_PWR_CON 0x0284 /* MT6735 */ #define SPM_CONN_PWR_CON 0x0280 #define SPM_VEN2_PWR_CON 0x0298 #define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */ @@ -57,11 +59,13 @@ #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_STATUS_MD1 BIT(0) #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) #define PWR_STATUS_ISP BIT(5) #define PWR_STATUS_VDEC BIT(7) +#define PWR_STATUS_VEN BIT(8) /* MT6735 */ #define PWR_STATUS_BDP BIT(14) #define PWR_STATUS_ETH BIT(15) #define PWR_STATUS_HIF BIT(16) @@ -750,6 +754,73 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = { {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, }; +/* + * MT6735 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt6735[] = { + [MT6735_POWER_DOMAIN_MD1] = { + .name = "md1", + .sta_mask = PWR_STATUS_MD1, + .ctl_offs = SPM_MD1_PWR_CON, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = 0, + .clk_id = {CLK_NONE}, + .bus_prot_mask = (BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28)), + }, + [MT6735_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = 0, + .clk_id = {CLK_NONE}, + .bus_prot_mask = (BIT(2) | BIT(8)), + }, + [MT6735_POWER_DOMAIN_DIS] = { + .name = "dis", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + .bus_prot_mask = (BIT(1)), + }, + [MT6735_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + .bus_prot_mask = BIT(14), + }, + [MT6735_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .clk_id = {CLK_NONE}, + }, + [MT6735_POWER_DOMAIN_VDE] = { + .name = "vde", + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .clk_id = {CLK_NONE}, + }, + [MT6735_POWER_DOMAIN_VEN] = { + .name = "ven", + .sta_mask = PWR_STATUS_VEN, + .ctl_offs = SPM_VEN_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_NONE}, + }, +}; + /* * MT6797 power domain support */ @@ -1033,6 +1104,16 @@ static const struct scp_soc_data mt2712_data = { .bus_prot_reg_update = false, }; +static const struct scp_soc_data mt6735_data = { + .domains = scp_domain_data_mt6735, + .num_domains = ARRAY_SIZE(scp_domain_data_mt6735), + .regs = { + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + }, + .bus_prot_reg_update = true, +}; + static const struct scp_soc_data mt6797_data = { .domains = scp_domain_data_mt6797, .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), @@ -1088,6 +1169,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { }, { .compatible = "mediatek,mt2712-scpsys", .data = &mt2712_data, + }, { + .compatible = "mediatek,mt6735-scpsys", + .data = &mt6735_data, }, { .compatible = "mediatek,mt6797-scpsys", .data = &mt6797_data,