diff mbox series

[v1,05/25] arm64: dts: colibri-imx8x: Add atmel pinctrl groups

Message ID 20230308125300.58244-6-dev@pschenker.ch (mailing list archive)
State New, archived
Headers show
Series Update Colibri iMX8X Devicetrees | expand

Commit Message

Philippe Schenker March 8, 2023, 12:52 p.m. UTC 
From: Philippe Schenker <philippe.schenker@toradex.com>

Add pinctrl groups for enabling atmel touchscreen support.
Remove the pads out of pinctrl_hog0 as they now can be enabled more
specific using pinctrl_atmel_conn label.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---

 .../boot/dts/freescale/imx8x-colibri.dtsi      | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 7fea99206020..0b84b65c846a 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -134,6 +134,22 @@  pinctrl_adc0: adc0grp {
 			   <IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60>;		/* SODIMM   2 */
 	};
 
+	/* Atmel MXT touchsceen + Capacitive Touch Adapter */
+	/* NOTE: This pingroup conflicts with pingroups
+	 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
+	 * simultaneously.
+	 */
+	pinctrl_atmel_adap: atmeladaptergrp {
+		fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22			0x21>,		/* SODIMM  30 */
+			   <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21			0x4000021>;	/* SODIMM  28 */
+	};
+
+	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+	pinctrl_atmel_conn: atmelconnectorgrp {
+		fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x4000021>,	/* SODIMM 107 */
+			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x21>;		/* SODIMM 106 */
+	};
+
 	pinctrl_can_int: canintgrp {
 		fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40>;		/* SODIMM  73 */
 	};
@@ -214,12 +230,10 @@  pinctrl_hog0: hog0grp {
 			   <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20>,		/* SODIMM  69 */
 			   <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20>,		/* SODIMM  99 */
 			   <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20>,		/* SODIMM 105 */
-			   <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20>,		/* SODIMM 107 */
 			   <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20>,		/* SODIMM  98 */
 			   <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22			0x20>,		/* SODIMM 102 */
 			   <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17			0x20>,		/* SODIMM  95 */
 			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>,		/* SODIMM 104 */
-			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20>,		/* SODIMM 106 */
 			   <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27			0x20>,		/* SODIMM  97 */
 			   <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26			0x20>,		/* SODIMM  79 */
 			   <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25			0x20>,		/* SODIMM 103 */