Message ID | 20230309145246.22787-5-joey.gouly@arm.com (mailing list archive) |
---|---|
State | New, archived |
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Thu, 9 Mar 2023 14:52:52 +0000 From: Joey Gouly <joey.gouly@arm.com> To: <linux-arm-kernel@lists.infradead.org> CC: <nd@arm.com>, <broonie@kernel.org>, <catalin.marinas@arm.com>, <james.morse@arm.com>, <joey.gouly@arm.com>, <mark.rutland@arm.com>, <maz@kernel.org>, <oliver.upton@linux.dev>, <suzuki.poulose@arm.com>, <will@kernel.org>, <yuzenghui@huawei.com> Subject: [PATCH v1 04/18] arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension Date: Thu, 9 Mar 2023 14:52:32 +0000 Message-ID: <20230309145246.22787-5-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230309145246.22787-1-joey.gouly@arm.com> References: <20230309145246.22787-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: VI1EUR03FT044:EE_|VI1PR08MB10297:EE_|VI1EUR03FT042:EE_|VE1PR08MB5630:EE_ X-MS-Office365-Filtering-Correlation-Id: 633ee1cd-944d-4afc-1093-08db20ae1ca1 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Permission Indirection Extension
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expand
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On Thu, Mar 09, 2023 at 02:52:32PM +0000, Joey Gouly wrote: > Add the trap bit definitions for nPIR_EL1 and nPIRE0_EL1. > /* HFG[WR]TR_EL2 bit definitions */ > +#define HFGxTR_EL2_nPIR_EL0_SHIFT 58 > +#define HFGxTR_EL2_nPIR_EL0_MASK BIT_MASK(HFGxTR_EL2_nPIR_EL0_SHIFT) > +#define HFGxTR_EL2_nPIREO_EL0_SHIFT 57 > +#define HFGxTR_EL2_nPIREO_EL0_MASK BIT_MASK(HFGxTR_EL2_nPIREO_EL0_SHIFT) Similarly please add new bits by syncing with the latest XML, in this case you could pick up the patch I posted the other day for this.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9e3ecba3c4e6..cb9e387e39e0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -759,6 +759,10 @@ #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) /* HFG[WR]TR_EL2 bit definitions */ +#define HFGxTR_EL2_nPIR_EL0_SHIFT 58 +#define HFGxTR_EL2_nPIR_EL0_MASK BIT_MASK(HFGxTR_EL2_nPIR_EL0_SHIFT) +#define HFGxTR_EL2_nPIREO_EL0_SHIFT 57 +#define HFGxTR_EL2_nPIREO_EL0_MASK BIT_MASK(HFGxTR_EL2_nPIREO_EL0_SHIFT) #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55 #define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT) #define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
Add the trap bit definitions for nPIR_EL1 and nPIRE0_EL1. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> --- arch/arm64/include/asm/sysreg.h | 4 ++++ 1 file changed, 4 insertions(+)