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Thu, 9 Mar 2023 14:52:52 +0000 From: Joey Gouly To: CC: , , , , , , , , , , Subject: [PATCH v1 04/18] arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension Date: Thu, 9 Mar 2023 14:52:32 +0000 Message-ID: <20230309145246.22787-5-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230309145246.22787-1-joey.gouly@arm.com> References: <20230309145246.22787-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: VI1EUR03FT044:EE_|VI1PR08MB10297:EE_|VI1EUR03FT042:EE_|VE1PR08MB5630:EE_ X-MS-Office365-Filtering-Correlation-Id: 633ee1cd-944d-4afc-1093-08db20ae1ca1 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: PK2gWfC3ecXiR95CUZGi73oyGPYS5iHV1liVuyooTqDPk4tUpC6Yn+EojUS0XneMnRG5bq6HMhJxkKOVAHGp5Z+0GAavD492VZCOFdRJYQ4M68QxzKgC67g2zs5Zh33z0UiLEak7bKFZkmR7ehjjKcvvQ++I/34Ji1rWM+wgHAENPXj4sLVG9o1Sf3bsuCgf63Wadabi6EsfCDLS+o8g06FzdNvdBLvzdkI2esBJKNpPpKUAfy5BEGnvX1o/SpekOwXF28Sg+e0bY/iVpJOyhYhEaEsfESqtjmcPXOhkNc8zx/Lk1F5V+A3qHbFr21ks/a4FcEo45Y90wpFzCyGrPqLP8hFXV2TKuT0BZuSCENxrEhseuloCVTReIaEUdSfIuSEFRwD7/2NEXYlgmpunJfdv/W8MON/NdKWXuaVG++Cr4qnBIXountOAOO8Pv/nN5spcb1b7KKZftfW6q7RjTxIq51IlkHsdaUg/vlZVRPPL+B4QS36qWZGLPQEwceFnVQSw7xpAZp/+6WOQ2U0zqwb2gXyIRr2Fp4vAwdtTFbrVdlINGi7GqbGr/zMVzZNFx570EZH3QowGalxNZKHNryT84fQBeJRRV2GuvcT4xnFbv4RUWFp4rByjNgUYSBWaSAIPMybyPPrHi+pmfyDNgFb0MaEvKhr1yEeGOQCEDSDVcaYE8bshcWoKuAaIcW2HyFYZUX8Dr+vEaCUrG32PsA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199018)(36840700001)(46966006)(47076005)(336012)(426003)(82310400005)(2616005)(54906003)(316002)(36756003)(36860700001)(1076003)(7696005)(356005)(86362001)(478600001)(40480700001)(26005)(82740400003)(81166007)(6666004)(186003)(19627235002)(5660300002)(4326008)(41300700001)(6916009)(2906002)(70586007)(44832011)(8936002)(8676002)(70206006)(4744005)(36900700001);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the trap bit definitions for nPIR_EL1 and nPIRE0_EL1. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown --- arch/arm64/include/asm/sysreg.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9e3ecba3c4e6..cb9e387e39e0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -759,6 +759,10 @@ #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) /* HFG[WR]TR_EL2 bit definitions */ +#define HFGxTR_EL2_nPIR_EL0_SHIFT 58 +#define HFGxTR_EL2_nPIR_EL0_MASK BIT_MASK(HFGxTR_EL2_nPIR_EL0_SHIFT) +#define HFGxTR_EL2_nPIREO_EL0_SHIFT 57 +#define HFGxTR_EL2_nPIREO_EL0_MASK BIT_MASK(HFGxTR_EL2_nPIREO_EL0_SHIFT) #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55 #define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT) #define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54