| Message ID | 20230310173657.57228-2-joey.gouly@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/2] aarch64: enable access to TCR2_ELx | expand |
On Fri, Mar 10, 2023 at 05:36:57PM +0000, Joey Gouly wrote: > + if (mrs_field(ID_AA64MMFR3_EL1, S1PIE)) > + scr |= SCR_EL3_PIEN; > + This is needed for all of S[12]_{PIE,POE} - the rest could be added incrementally of course.
On Tue, Mar 14, 2023 at 04:24:28PM +0000, Mark Brown wrote: > On Fri, Mar 10, 2023 at 05:36:57PM +0000, Joey Gouly wrote: > > > + if (mrs_field(ID_AA64MMFR3_EL1, S1PIE)) > > + scr |= SCR_EL3_PIEN; > > + > > This is needed for all of S[12]_{PIE,POE} - the rest could be added > incrementally of course. Given we know about that now, I'd prefer if we handled them all now, e.g. if (mrs_field(ID_AA64MMFR3_EL1, S1PIE) || mrs_field(ID_AA64MMFR3_EL1, S2PIE) || mrs_field(ID_AA64MMFR3_EL1, S1POE) || mrs_field(ID_AA64MMFR3_EL1, S2POE)) scr |= SCR_EL3_PIEN; ... or do the same as with pauth and have a helper: static inline bool cpu_has_permission_indirection(void) { const unsigned long mask = ID_AA64MMFR3_EL1_S1PIE | ID_AA64MMFR3_EL1_S2PIE | ID_AA64MMFR3_EL1_S1POE | ID_AA64MMFR3_EL1_S2POE); return mrs(ID_AA64MMFR3_EL1) & mask } .. and then: if (cpu_has_permission_indirection()) scr |= SCR_EL3_PIEN; For consistency with pauth I guess the second option is best. Thanks, Mark.
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 3686e08..fe732dc 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -52,6 +52,7 @@ #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) +#define SCR_EL3_PIEN BIT(45) #define HCR_EL2_RES1 BIT(1) @@ -75,6 +76,7 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) #define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) +#define ID_AA64MMFR3_EL1_S1PIE BITS(11, 8) #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index f004e41..0fd7535 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -67,6 +67,9 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR3_EL1, TCRX)) scr |= SCR_EL3_TCR2EN; + if (mrs_field(ID_AA64MMFR3_EL1, S1PIE)) + scr |= SCR_EL3_PIEN; + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA;
Allow lower ELs to access the registers associated with the Permission Indirection Extension. Signed-off-by: Joey Gouly <joey.gouly@arm.com> --- arch/aarch64/include/asm/cpu.h | 2 ++ arch/aarch64/init.c | 3 +++ 2 files changed, 5 insertions(+)