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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id o9-20020a05651238a900b004db48ae69cbsm18134lft.206.2023.03.13.09.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 09:47:55 -0700 (PDT) From: Konrad Dybcio Date: Mon, 13 Mar 2023 17:44:20 +0100 Subject: [PATCH v3 5/6] arm64: dts: qcom: sm8250: Add qcom,smmu-500 to Adreno SMMU MIME-Version: 1.0 Message-Id: <20230313-topic-gpu_smmu_bindings-v3-5-66ab655fbfd5@linaro.org> References: <20230313-topic-gpu_smmu_bindings-v3-0-66ab655fbfd5@linaro.org> In-Reply-To: <20230313-topic-gpu_smmu_bindings-v3-0-66ab655fbfd5@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678726067; l=837; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=fDzp/6YnfTrRmkZHxWUQXIGpdeCMrs4IC6LBNSCvx9M=; b=oYA8x3dZFacSEaO5HD4/R9aKdOdYV+N6P3elUE4qOCAKdBKuuo6Su2jDD8IPb3edElmfRLKLMZyH L2Aod54rAhAs9XlBwWbkSAk6NaEL97TbuOwcow/A64HPvWlVaIqL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230313_094800_043184_A8DFD995 X-CRM114-Status: GOOD ( 10.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2f0e460acccd..044c8c1c9d48 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2656,7 +2656,8 @@ gpucc: clock-controller@3d90000 { }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>;